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[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 1471 and 1486

Rev 1471	Rev 1486
Line 67...	Line 67...
`spr_write_ttmr (value);`	`spr_write_ttmr (value);`
`break;`	`break;`
`/* Data cache simulateing stuff */`	`/* Data cache simulateing stuff */`
`case SPR_DCBPR:`	`case SPR_DCBPR:`
`if(value) {`	`if(value) {`
`dc_simulate_read(value, 4);`	`/* FIXME: The arch. manual says "DCBPR is written with the effective`
	`* address" which suggests it is written with a _virtual_ address,`
	`* but it seems that the cache sits behind the mmu. How is this`
	`* address translated then? */`
	`dc_simulate_read(value, value, 4);`
`cpu_state.sprs[SPR_DCBPR] = 0;`	`cpu_state.sprs[SPR_DCBPR] = 0;`
`}`	`}`
`break;`	`break;`
`case SPR_DCBFR:`	`case SPR_DCBFR:`
`if(value != -1) {`	`if(value != -1) {`
Line 92...	Line 96...
`cpu_state.sprs[SPR_DCBLR] = 0;`	`cpu_state.sprs[SPR_DCBLR] = 0;`
`break;`	`break;`
`/* Instruction cache simulateing stuff */`	`/* Instruction cache simulateing stuff */`
`case SPR_ICBPR:`	`case SPR_ICBPR:`
`if(value) {`	`if(value) {`
`ic_simulate_fetch(value);`	`/* FIXME: The arch. manual says "ICBPR is written with the effective`
	`* address" which suggests it is written with a _virtual_ address,`
	`* but it seems that the cache sits behind the mmu. How is this`
	`* address translated then? */`
	`ic_simulate_fetch(value, value);`
`cpu_state.sprs[SPR_ICBPR] = 0;`	`cpu_state.sprs[SPR_ICBPR] = 0;`
`}`	`}`
`break;`	`break;`
`case SPR_ICBIR:`	`case SPR_ICBIR:`
`if(value) {`	`if(value) {`