| Line 48... |
Line 48... |
int audio_cnt = 0;
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int audio_cnt = 0;
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static FILE *fo = 0;
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static FILE *fo = 0;
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/* Set a specific SPR with a value. */
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/* Set a specific SPR with a value. */
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void
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void
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mtspr(uint16_t regno, const sprword value)
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mtspr(uint16_t regno, const uorreg_t value)
|
{
|
{
|
sprword prev_val;
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uorreg_t prev_val;
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|
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regno %= MAX_SPRS;
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regno %= MAX_SPRS;
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prev_val = cpu_state.sprs[regno];
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prev_val = cpu_state.sprs[regno];
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cpu_state.sprs[regno] = value;
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cpu_state.sprs[regno] = value;
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| Line 212... |
Line 212... |
}
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}
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break;
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break;
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}
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}
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}
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}
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|
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/* Get a specific SPR. */
|
|
uorreg_t mfspr(const uint16_t regno)
|
|
{
|
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extern oraddr_t pcprev;
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|
|
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switch (regno) {
|
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case SPR_NPC:
|
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return cpu_state.pc;
|
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case SPR_PPC:
|
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return pcprev;
|
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case SPR_TTCR:
|
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return spr_read_ttcr();
|
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default:
|
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/* Links to GPRS */
|
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if(regno >= 0x0400 && regno < 0x0420)
|
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return cpu_state.reg[regno - 0x0400];
|
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else if (regno < MAX_SPRS)
|
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return cpu_state.sprs[regno];
|
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}
|
|
if (config.sim.verbose)
|
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PRINTF ("WARNING: read out of SPR range %08X\n", regno);
|
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return 0;
|
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}
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|
|
/* Show status of important SPRs. */
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/* Show status of important SPRs. */
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void sprs_status()
|
void sprs_status(void)
|
{
|
{
|
PRINTF("VR : 0x%.8lx UPR : 0x%.8lx\n", mfspr(SPR_VR), mfspr(SPR_UPR));
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PRINTF("VR : 0x%"PRIxREG" UPR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_VR],
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PRINTF("SR : 0x%.8lx\n", mfspr(SPR_SR));
|
cpu_state.sprs[SPR_UPR]);
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PRINTF("MACLO: 0x%.8lx MACHI: 0x%.8lx\n", mfspr(SPR_MACLO), mfspr(SPR_MACHI));
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PRINTF("SR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_SR]);
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PRINTF("EPCR0: 0x%.8lx EPCR1: 0x%.8lx\n", mfspr(SPR_EPCR_BASE), mfspr(SPR_EPCR_BASE+1));
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PRINTF("MACLO: 0x%"PRIxREG" MACHI: 0x%"PRIxREG"\n",
|
PRINTF("EEAR0: 0x%.8lx EEAR1: 0x%.8lx\n", mfspr(SPR_EEAR_BASE), mfspr(SPR_EEAR_BASE+1));
|
cpu_state.sprs[SPR_MACLO], cpu_state.sprs[SPR_MACHI]);
|
PRINTF("ESR0 : 0x%.8lx ESR1 : 0x%.8lx\n", mfspr(SPR_ESR_BASE), mfspr(SPR_ESR_BASE+1));
|
PRINTF("EPCR0: 0x%"PRIxADDR" EPCR1: 0x%"PRIxADDR"\n",
|
PRINTF("TTMR : 0x%.8lx TTCR : 0x%.8lx\n", mfspr(SPR_TTMR), mfspr(SPR_TTCR));
|
cpu_state.sprs[SPR_EPCR_BASE], cpu_state.sprs[SPR_EPCR_BASE+1]);
|
PRINTF("PICMR: 0x%.8lx PICSR: 0x%.8lx\n", mfspr(SPR_PICMR), mfspr(SPR_PICSR));
|
PRINTF("EEAR0: 0x%"PRIxADDR" EEAR1: 0x%"PRIxADDR"\n",
|
PRINTF("PPC: 0x%.8lx NPC : 0x%.8lx\n", mfspr(SPR_PPC), mfspr(SPR_NPC));
|
cpu_state.sprs[SPR_EEAR_BASE], cpu_state.sprs[SPR_EEAR_BASE+1]);
|
|
PRINTF("ESR0 : 0x%"PRIxREG" ESR1 : 0x%"PRIxREG"\n",
|
|
cpu_state.sprs[SPR_ESR_BASE], cpu_state.sprs[SPR_ESR_BASE+1]);
|
|
PRINTF("TTMR : 0x%"PRIxREG" TTCR : 0x%"PRIxREG"\n",
|
|
cpu_state.sprs[SPR_TTMR], cpu_state.sprs[SPR_TTCR]);
|
|
PRINTF("PICMR: 0x%"PRIxREG" PICSR: 0x%"PRIxREG"\n",
|
|
cpu_state.sprs[SPR_PICMR], cpu_state.sprs[SPR_PICSR]);
|
|
PRINTF("PPC: 0x%"PRIxADDR" NPC : 0x%"PRIxADDR"\n",
|
|
cpu_state.sprs[SPR_PPC], cpu_state.sprs[SPR_NPC]);
|
}
|
}
|
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No newline at end of file
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No newline at end of file
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