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[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 1551 and 1557
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| Rev 1551 |
Rev 1557 |
| Line 37... |
Line 37... |
#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "dcache_model.h"
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#include "dcache_model.h"
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#include "icache_model.h"
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#include "icache_model.h"
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#include "tick.h"
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#include "dmmu.h"
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#include "immu.h"
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#include "debug.h"
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#include "debug.h"
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DEFAULT_DEBUG_CHANNEL(spr);
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DEFAULT_DEBUG_CHANNEL(spr);
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DECLARE_DEBUG_CHANNEL(immu);
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DECLARE_DEBUG_CHANNEL(immu);
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| Line 92... |
Line 95... |
break;
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break;
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/* Instruction cache simulateing stuff */
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/* Instruction cache simulateing stuff */
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case SPR_ICBPR:
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case SPR_ICBPR:
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/* FIXME: The arch manual does not say what happens when an invalid memory
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/* FIXME: The arch manual does not say what happens when an invalid memory
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* location is specified. I guess the same as for the DCBPR register */
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* location is specified. I guess the same as for the DCBPR register */
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ic_simulate_fetch(peek_into_itlb(value, 1), value);
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ic_simulate_fetch(peek_into_itlb(value), value);
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cpu_state.sprs[SPR_ICBPR] = 0;
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cpu_state.sprs[SPR_ICBPR] = 0;
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break;
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break;
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case SPR_ICBIR:
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case SPR_ICBIR:
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ic_inv(value);
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ic_inv(value);
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cpu_state.sprs[SPR_ICBIR] = 0;
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cpu_state.sprs[SPR_ICBIR] = 0;
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