| Line 470... |
Line 470... |
fprintf(runtime.sim.fexe_log, "\n");
|
fprintf(runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "GPR%2u: %"PRIxREG" ", i,
|
fprintf (runtime.sim.fexe_log, "GPR%2u: %"PRIxREG" ", i,
|
cpu_state.reg[i]);
|
cpu_state.reg[i]);
|
}
|
}
|
fprintf (runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
|
fprintf (runtime.sim.fexe_log, "SR : %.8"PRIx32" ",
|
fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
|
cpu_state.sprs[SPR_SR]);
|
fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
|
fprintf (runtime.sim.fexe_log, "EPCR0: %"PRIxADDR" ",
|
fprintf (runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));
|
cpu_state.sprs[SPR_EPCR_BASE]);
|
|
fprintf (runtime.sim.fexe_log, "EEAR0: %"PRIxADDR" ",
|
|
cpu_state.sprs[SPR_EEAR_BASE]);
|
|
fprintf (runtime.sim.fexe_log, "ESR0 : %.8"PRIx32"\n",
|
|
cpu_state.sprs[SPR_ESR_BASE]);
|
break;
|
break;
|
case EXE_LOG_SIMPLE:
|
case EXE_LOG_SIMPLE:
|
case EXE_LOG_SOFTWARE:
|
case EXE_LOG_SOFTWARE:
|
{
|
{
|
extern char *disassembled;
|
extern char *disassembled;
|
| Line 594... |
Line 598... |
|
|
#if SET_OV_FLAG
|
#if SET_OV_FLAG
|
/* Check for range exception */
|
/* Check for range exception */
|
if((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) &&
|
if((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) &&
|
(cpu_state.sprs[SPR_SR] & SPR_SR_OV))
|
(cpu_state.sprs[SPR_SR] & SPR_SR_OV))
|
except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));
|
except_handle (EXCEPT_RANGE, cpu_state.sprs[SPR_EEAR_BASE]);
|
#endif
|
#endif
|
|
|
if(breakpoint)
|
if(breakpoint)
|
except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
|
except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
|
}
|
}
|
|
|
/* Reset the CPU */
|
/* Reset the CPU */
|
void cpu_reset()
|
void cpu_reset()
|
{
|
{
|
| Line 682... |
Line 686... |
except_pending = 0;
|
except_pending = 0;
|
return 0;
|
return 0;
|
}
|
}
|
|
|
if(breakpoint) {
|
if(breakpoint) {
|
except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
|
except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
|
update_pc();
|
update_pc();
|
except_pending = 0;
|
except_pending = 0;
|
return 0;
|
return 0;
|
}
|
}
|
|
|
