| Line 307... |
Line 307... |
runtime.sim.cycles - runtime.sim.reset_cycles,
|
runtime.sim.cycles - runtime.sim.reset_cycles,
|
runtime.cpu.instructions - runtime.cpu.reset_instructions);
|
runtime.cpu.instructions - runtime.cpu.reset_instructions);
|
if (config.debug.gdb_enabled)
|
if (config.debug.gdb_enabled)
|
set_stall_state (1);
|
set_stall_state (1);
|
else
|
else
|
runtime.sim.cont_run = 0;
|
sim_done();
|
break;
|
break;
|
case NOP_CNT_RESET:
|
case NOP_CNT_RESET:
|
PRINTF("****************** counters reset ******************\n");
|
PRINTF("****************** counters reset ******************\n");
|
PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
|
PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
|
PRINTF("****************** counters reset ******************\n");
|
PRINTF("****************** counters reset ******************\n");
|
| Line 412... |
Line 412... |
|
|
if (mfspr(SPR_SR) & SPR_SR_SM)
|
if (mfspr(SPR_SR) & SPR_SR_SM)
|
mtspr(regno, value);
|
mtspr(regno, value);
|
else {
|
else {
|
PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
|
PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
|
runtime.sim.cont_run = 0;
|
sim_done();
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_mfspr) {
|
INSTRUCTION (l_mfspr) {
|
uint16_t regno = PARAM1 + PARAM2;
|
uint16_t regno = PARAM1 + PARAM2;
|
uorreg_t value = mfspr(regno);
|
uorreg_t value = mfspr(regno);
|
| Line 428... |
Line 428... |
if (mfspr(SPR_SR) & SPR_SR_SM)
|
if (mfspr(SPR_SR) & SPR_SR_SM)
|
SET_PARAM0(value);
|
SET_PARAM0(value);
|
else {
|
else {
|
SET_PARAM0(0);
|
SET_PARAM0(0);
|
PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
|
PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
|
runtime.sim.cont_run = 0;
|
sim_done();
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_sys) {
|
INSTRUCTION (l_sys) {
|
except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE));
|
except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE));
|
}
|
}
|
