| Line 297... |
Line 297... |
if (config.sim.profile)
|
if (config.sim.profile)
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fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
|
fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
|
cpu_state.pc_delay);
|
cpu_state.pc_delay);
|
}
|
}
|
INSTRUCTION (l_rfe) {
|
INSTRUCTION (l_rfe) {
|
pcnext = mfspr(SPR_EPCR_BASE);
|
pcnext = cpu_state.sprs[SPR_EPCR_BASE];
|
mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
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mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
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}
|
}
|
INSTRUCTION (l_nop) {
|
INSTRUCTION (l_nop) {
|
oraddr_t stackaddr;
|
oraddr_t stackaddr;
|
uint32_t k = PARAM0;
|
uint32_t k = PARAM0;
|
switch (k) {
|
switch (k) {
|
| Line 449... |
Line 449... |
|
|
if (runtime.sim.fspr_log) {
|
if (runtime.sim.fspr_log) {
|
fprintf(runtime.sim.fspr_log, "Write to SPR : [%08"PRIx16"] <- [%08"PRIx32"]\n", regno, value);
|
fprintf(runtime.sim.fspr_log, "Write to SPR : [%08"PRIx16"] <- [%08"PRIx32"]\n", regno, value);
|
}
|
}
|
|
|
if (mfspr(SPR_SR) & SPR_SR_SM)
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
|
mtspr(regno, value);
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mtspr(regno, value);
|
else {
|
else {
|
PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
|
PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
|
sim_done();
|
sim_done();
|
}
|
}
|
| Line 464... |
Line 464... |
|
|
if (runtime.sim.fspr_log) {
|
if (runtime.sim.fspr_log) {
|
fprintf(runtime.sim.fspr_log, "Read from SPR : [%08"PRIx16"] -> [%08"PRIx32"]\n", regno, value);
|
fprintf(runtime.sim.fspr_log, "Read from SPR : [%08"PRIx16"] -> [%08"PRIx32"]\n", regno, value);
|
}
|
}
|
|
|
if (mfspr(SPR_SR) & SPR_SR_SM)
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
|
SET_PARAM0(value);
|
SET_PARAM0(value);
|
else {
|
else {
|
SET_PARAM0(0);
|
SET_PARAM0(0);
|
PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
|
PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
|
sim_done();
|
sim_done();
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_sys) {
|
INSTRUCTION (l_sys) {
|
except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE));
|
except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
|
}
|
}
|
INSTRUCTION (l_trap) {
|
INSTRUCTION (l_trap) {
|
/* TODO: some SR related code here! */
|
/* TODO: some SR related code here! */
|
except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
|
except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
|
}
|
}
|
INSTRUCTION (l_mac) {
|
INSTRUCTION (l_mac) {
|
sprword lo, hi;
|
uorreg_t lo, hi;
|
LONGEST l;
|
LONGEST l;
|
orreg_t x, y;
|
orreg_t x, y;
|
|
|
lo = mfspr (SPR_MACLO);
|
lo = cpu_state.sprs[SPR_MACLO];
|
hi = mfspr (SPR_MACHI);
|
hi = cpu_state.sprs[SPR_MACHI];
|
x = PARAM0;
|
x = PARAM0;
|
y = PARAM1;
|
y = PARAM1;
|
PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
|
PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
|
l = (ULONGEST)lo | ((LONGEST)hi << 32);
|
l = (ULONGEST)lo | ((LONGEST)hi << 32);
|
l += (LONGEST) x * (LONGEST) y;
|
l += (LONGEST) x * (LONGEST) y;
|
|
|
/* This implementation is very fast - it needs only one cycle for mac. */
|
/* This implementation is very fast - it needs only one cycle for mac. */
|
lo = ((ULONGEST)l) & 0xFFFFFFFF;
|
lo = ((ULONGEST)l) & 0xFFFFFFFF;
|
hi = ((LONGEST)l) >> 32;
|
hi = ((LONGEST)l) >> 32;
|
mtspr (SPR_MACLO, lo);
|
cpu_state.sprs[SPR_MACLO] = lo;
|
mtspr (SPR_MACHI, hi);
|
cpu_state.sprs[SPR_MACHI] = hi;
|
PRINTF ("(%08lx,%08lx)\n", hi, lo);
|
PRINTF ("(%08lx,%08lx)\n", hi, lo);
|
}
|
}
|
INSTRUCTION (l_msb) {
|
INSTRUCTION (l_msb) {
|
sprword lo, hi;
|
uorreg_t lo, hi;
|
LONGEST l;
|
LONGEST l;
|
orreg_t x, y;
|
orreg_t x, y;
|
|
|
lo = mfspr (SPR_MACLO);
|
lo = cpu_state.sprs[SPR_MACLO];
|
hi = mfspr (SPR_MACHI);
|
hi = cpu_state.sprs[SPR_MACHI];
|
x = PARAM0;
|
x = PARAM0;
|
y = PARAM1;
|
y = PARAM1;
|
|
|
PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
|
PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
|
|
|
| Line 517... |
Line 517... |
l -= x * y;
|
l -= x * y;
|
|
|
/* This implementation is very fast - it needs only one cycle for msb. */
|
/* This implementation is very fast - it needs only one cycle for msb. */
|
lo = ((ULONGEST)l) & 0xFFFFFFFF;
|
lo = ((ULONGEST)l) & 0xFFFFFFFF;
|
hi = ((LONGEST)l) >> 32;
|
hi = ((LONGEST)l) >> 32;
|
mtspr (SPR_MACLO, lo);
|
cpu_state.sprs[SPR_MACLO] = lo;
|
mtspr (SPR_MACHI, hi);
|
cpu_state.sprs[SPR_MACHI] = hi;
|
PRINTF ("(%08lx,%08lx)\n", hi, lo);
|
PRINTF ("(%08lx,%08lx)\n", hi, lo);
|
}
|
}
|
INSTRUCTION (l_macrc) {
|
INSTRUCTION (l_macrc) {
|
sprword lo, hi;
|
uorreg_t lo, hi;
|
LONGEST l;
|
LONGEST l;
|
/* No need for synchronization here -- all MAC instructions are 1 cycle long. */
|
/* No need for synchronization here -- all MAC instructions are 1 cycle long. */
|
lo = mfspr (SPR_MACLO);
|
lo = cpu_state.sprs[SPR_MACLO];
|
hi = mfspr (SPR_MACHI);
|
hi = cpu_state.sprs[SPR_MACHI];
|
l = (ULONGEST) lo | ((LONGEST)hi << 32);
|
l = (ULONGEST) lo | ((LONGEST)hi << 32);
|
l >>= 28;
|
l >>= 28;
|
//PRINTF ("<%08x>\n", (unsigned long)l);
|
//PRINTF ("<%08x>\n", (unsigned long)l);
|
SET_PARAM0((orreg_t)l);
|
SET_PARAM0((orreg_t)l);
|
mtspr (SPR_MACLO, 0);
|
cpu_state.sprs[SPR_MACLO] = 0;
|
mtspr (SPR_MACHI, 0);
|
cpu_state.sprs[SPR_MACHI] = 0;
|
}
|
}
|
INSTRUCTION (l_cmov) {
|
INSTRUCTION (l_cmov) {
|
SET_PARAM0(flag ? PARAM1 : PARAM2);
|
SET_PARAM0(flag ? PARAM1 : PARAM2);
|
}
|
}
|
INSTRUCTION (l_ff1) {
|
INSTRUCTION (l_ff1) {
|
