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https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Diff between revs 1513 and 1537
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| Rev 1513 |
Rev 1537 |
| Line 432... |
Line 432... |
}
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}
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INSTRUCTION (l_mtspr) {
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INSTRUCTION (l_mtspr) {
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uint16_t regno = PARAM0 + PARAM2;
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uint16_t regno = PARAM0 + PARAM2;
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uorreg_t value = PARAM1;
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uorreg_t value = PARAM1;
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if (runtime.sim.fspr_log) {
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fprintf(runtime.sim.fspr_log, "Write to SPR : [%08"PRIx16"] <- [%08"PRIx32"]\n", regno, value);
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}
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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mtspr(regno, value);
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mtspr(regno, value);
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else {
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else {
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PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
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PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
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sim_done();
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sim_done();
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| Line 447... |
Line 443... |
}
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}
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INSTRUCTION (l_mfspr) {
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INSTRUCTION (l_mfspr) {
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uint16_t regno = PARAM1 + PARAM2;
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uint16_t regno = PARAM1 + PARAM2;
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uorreg_t value = mfspr(regno);
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uorreg_t value = mfspr(regno);
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if (runtime.sim.fspr_log) {
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fprintf(runtime.sim.fspr_log, "Read from SPR : [%08"PRIx16"] -> [%08"PRIx32"]\n", regno, value);
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}
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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SET_PARAM0(value);
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SET_PARAM0(value);
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else {
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else {
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SET_PARAM0(0);
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SET_PARAM0(0);
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PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
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PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
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