| Line 43... |
Line 43... |
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#include "i386_regs.h"
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#include "i386_regs.h"
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#include "dyn_rec.h"
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#include "dyn_rec.h"
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/* This must be here since the function in op_i386.h use this variable */
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register struct cpu_state *env asm(CPU_STATE_REG);
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register struct cpu_state *env asm(CPU_STATE_REG);
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#include "op_i386.h"
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#include "op_i386.h"
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/*
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/*
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| Line 108... |
Line 107... |
env->reg[(reg >> 10) & 0x1f] = t2;
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env->reg[(reg >> 10) & 0x1f] = t2;
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}
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}
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void do_sched_wrap(void)
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void do_sched_wrap(void)
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{
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{
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upd_sim_cycles();
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env->pc += 4;
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//runtime.cpu.instructions++;
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runtime.sim.cycles -= env->cycles_dec;
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scheduler.job_queue->time += env->cycles_dec;
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if(scheduler.job_queue->time <= 0) {
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save_t_bound(env->pc - 4);
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save_t_bound(env->pc - 4);
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do_scheduler();
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do_scheduler();
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}
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}
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}
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/* do_scheduler wrapper for instructions that are in the delay slot */
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/* do_scheduler wrapper for instructions that are in the delay slot */
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void do_sched_wrap_delay(void)
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void do_sched_wrap_delay(void)
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{
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{
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upd_sim_cycles();
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/* FIXME: Can't this be eliminated? */
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env->pc += 4;
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//runtime.cpu.instructions++;
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runtime.sim.cycles -= env->cycles_dec;
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scheduler.job_queue->time += env->cycles_dec;
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if(scheduler.job_queue->time <= 0)
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do_scheduler();
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do_scheduler();
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}
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}
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void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)
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void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)
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{
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{
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| Line 145... |
Line 154... |
}
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}
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__or_dynop void op_set_pc_pc_delay(void)
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__or_dynop void op_set_pc_pc_delay(void)
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{
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{
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env->sprs[SPR_PPC] = get_pc();
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env->sprs[SPR_PPC] = env->pc;
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/* pc_delay is pulled back 4 since imediatly after this is run, the scheduler
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/* pc_delay is pulled back 4 since imediatly after this is run, the scheduler
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* runs which also increments it by 4 */
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* runs which also increments it by 4 */
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set_pc(env->pc_delay - 4);
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env->pc = env->pc_delay - 4;
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}
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}
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__or_dynop void op_set_pc_delay_imm(void)
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__or_dynop void op_set_pc_delay_imm(void)
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{
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{
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env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
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env->pc_delay = env->pc + (orreg_t)OP_PARAM1;
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env->delay_insn = 1;
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env->delay_insn = 1;
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}
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}
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__or_dynop void op_set_pc_delay_pc(void)
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__or_dynop void op_set_pc_delay_pc(void)
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{
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{
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env->pc_delay = get_pc();
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env->pc_delay = env->pc;
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env->delay_insn = 1;
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env->delay_insn = 1;
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}
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}
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__or_dynop void op_clear_pc_delay(void)
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__or_dynop void op_clear_pc_delay(void)
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{
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{
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Line 180... |
env->delay_insn = 1;
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env->delay_insn = 1;
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}
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}
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__or_dynop void op_do_jump(void)
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__or_dynop void op_do_jump(void)
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{
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{
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do_jump(get_pc());
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do_jump(env->pc);
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}
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}
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__or_dynop void op_do_jump_delay(void)
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__or_dynop void op_do_jump_delay(void)
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{
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{
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do_jump(env->pc_delay);
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do_jump(env->pc_delay);
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Line 224... |
/* Used for the l.bf instruction. Therefore if the flag is not set, jump over
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/* Used for the l.bf instruction. Therefore if the flag is not set, jump over
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* all the jumping stuff */
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* all the jumping stuff */
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__or_dynop void op_check_flag(void)
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__or_dynop void op_check_flag(void)
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{
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{
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if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
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if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
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HANDLE_SCHED(do_sched_wrap, "no_sched_chk_flg");
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SPEEDY_CALL(do_sched_wrap);
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OP_JUMP(OP_PARAM1);
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OP_JUMP(OP_PARAM1);
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}
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}
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}
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}
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/* Used for l.bf if the delay slot instruction is on another page */
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/* Used for l.bf if the delay slot instruction is on another page */
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__or_dynop void op_check_flag_delay(void)
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__or_dynop void op_check_flag_delay(void)
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{
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{
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if(env->sprs[SPR_SR] & SPR_SR_F) {
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if(env->sprs[SPR_SR] & SPR_SR_F) {
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env->delay_insn = 1;
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env->delay_insn = 1;
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env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
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env->pc_delay = env->pc + (orreg_t)OP_PARAM1;
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}
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}
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}
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}
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/* Used for the l.bnf instruction. Therefore if the flag is set, jump over all
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/* Used for the l.bnf instruction. Therefore if the flag is set, jump over all
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* the jumping stuff */
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* the jumping stuff */
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__or_dynop void op_check_not_flag(void)
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__or_dynop void op_check_not_flag(void)
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{
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{
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if(env->sprs[SPR_SR] & SPR_SR_F) {
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if(env->sprs[SPR_SR] & SPR_SR_F) {
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HANDLE_SCHED(do_sched_wrap, "no_sched_chk_not_flg");
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SPEEDY_CALL(do_sched_wrap);
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OP_JUMP(OP_PARAM1);
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OP_JUMP(OP_PARAM1);
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}
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}
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}
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}
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/* Used for l.bnf if the delay slot instruction is on another page */
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/* Used for l.bnf if the delay slot instruction is on another page */
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__or_dynop void op_check_not_flag_delay(void)
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__or_dynop void op_check_not_flag_delay(void)
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{
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{
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if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
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if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
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env->delay_insn = 1;
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env->delay_insn = 1;
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env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
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env->pc_delay = env->pc + (orreg_t)OP_PARAM1;
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}
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}
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}
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}
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__or_dynop void op_add_pc(void)
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__or_dynop void op_add_pc(void)
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{
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{
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/* FIXME: Optimise */
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env->pc += OP_PARAM1;
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set_pc(get_pc() + OP_PARAM1);
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}
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}
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__or_dynop void op_nop_exit(void)
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__or_dynop void op_nop_exit(void)
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{
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{
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upd_sim_cycles();
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op_support_nop_exit();
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op_support_nop_exit();
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FORCE_RET;
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FORCE_RET;
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}
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}
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__or_dynop void op_nop_reset(void)
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__or_dynop void op_nop_reset(void)
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{
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{
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upd_sim_cycles();
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op_support_nop_reset();
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op_support_nop_reset();
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do_jump(EXCEPT_RESET);
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do_jump(EXCEPT_RESET);
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}
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}
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__or_dynop void op_nop_printf(void)
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__or_dynop void op_nop_printf(void)
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{
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{
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upd_sim_cycles();
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op_support_nop_printf();
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op_support_nop_printf();
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FORCE_RET;
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FORCE_RET;
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}
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}
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__or_dynop void op_nop_report(void)
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__or_dynop void op_nop_report(void)
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{
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{
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upd_sim_cycles();
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op_support_nop_report();
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op_support_nop_report();
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FORCE_RET;
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FORCE_RET;
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}
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}
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__or_dynop void op_nop_report_imm(void)
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__or_dynop void op_nop_report_imm(void)
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{
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{
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upd_sim_cycles();
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op_support_nop_report_imm(OP_PARAM1);
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op_support_nop_report_imm(OP_PARAM1);
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}
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}
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__or_dynop void op_analysis(void)
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__or_dynop void op_analysis(void)
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{
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{
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| Line 859... |
Line 862... |
#undef S_FUNC
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#undef S_FUNC
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#undef S_OP_NAME
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#undef S_OP_NAME
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__or_dynop void op_join_mem_cycles(void)
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__or_dynop void op_join_mem_cycles(void)
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{
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{
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join_mem_cycles();
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runtime.sim.cycles += runtime.sim.mem_cycles;
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scheduler.job_queue->time -= runtime.sim.mem_cycles;
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runtime.sim.mem_cycles = 0;
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}
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}
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__or_dynop void op_store_link_addr_gpr(void)
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__or_dynop void op_store_link_addr_gpr(void)
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{
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{
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env->reg[LINK_REGNO] = get_pc() + 8;
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env->reg[LINK_REGNO] = env->pc + 8;
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}
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}
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__or_dynop void op_prep_rfe(void)
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__or_dynop void op_prep_rfe(void)
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{
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{
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env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
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env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
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env->sprs[SPR_PPC] = get_pc();
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env->sprs[SPR_PPC] = env->pc;
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set_pc(env->sprs[SPR_EPCR_BASE] - 4);
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env->pc = env->sprs[SPR_EPCR_BASE] - 4;
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}
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}
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static inline void prep_except(oraddr_t epcr_base)
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static inline void prep_except(oraddr_t epcr_base)
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{
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{
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env->sprs[SPR_EPCR_BASE] = epcr_base;
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env->sprs[SPR_EPCR_BASE] = epcr_base;
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| Line 892... |
Line 897... |
env->sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */
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env->sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */
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}
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}
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__or_dynop void op_set_except_pc(void)
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__or_dynop void op_set_except_pc(void)
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{
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{
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set_pc(OP_PARAM1);
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env->pc = OP_PARAM1;
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}
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}
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/* Before the code in op_{sys,trap}{,_delay} gets run, the scheduler runs.
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/* Before the code in op_{sys,trap}{,_delay} gets run, the scheduler runs.
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* Therefore the pc will point to the instruction after the l.sys or l.trap
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* Therefore the pc will point to the instruction after the l.sys or l.trap
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* instruction */
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* instruction */
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__or_dynop void op_prep_sys_delay(void)
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__or_dynop void op_prep_sys_delay(void)
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{
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{
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env->delay_insn = 0;
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env->delay_insn = 0;
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prep_except(get_pc() - 4);
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prep_except(env->pc - 4);
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set_pc(EXCEPT_SYSCALL - 4);
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env->pc = EXCEPT_SYSCALL - 4;
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}
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}
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__or_dynop void op_prep_sys(void)
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__or_dynop void op_prep_sys(void)
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{
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{
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prep_except(get_pc() + 4);
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prep_except(env->pc + 4);
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set_pc(EXCEPT_SYSCALL - 4);
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env->pc = EXCEPT_SYSCALL - 4;
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}
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}
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__or_dynop void op_prep_trap_delay(void)
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__or_dynop void op_prep_trap_delay(void)
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{
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{
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env->delay_insn = 0;
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env->delay_insn = 0;
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prep_except(get_pc() - 4);
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prep_except(env->pc - 4);
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set_pc(EXCEPT_TRAP - 4);
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env->pc = EXCEPT_TRAP - 4;
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}
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}
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__or_dynop void op_prep_trap(void)
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__or_dynop void op_prep_trap(void)
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{
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{
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prep_except(get_pc());
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prep_except(env->pc);
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set_pc(EXCEPT_TRAP - 4);
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env->pc = EXCEPT_TRAP - 4;
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}
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}
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/* FIXME: This `instruction' should be split up like the l.trap and l.sys
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/* FIXME: This `instruction' should be split up like the l.trap and l.sys
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* instructions are done */
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* instructions are done */
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__or_dynop void op_illegal_delay(void)
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__or_dynop void op_illegal_delay(void)
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{
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{
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env->delay_insn = 0;
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env->delay_insn = 0;
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env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
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env->sprs[SPR_EEAR_BASE] = env->pc - 4;
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do_jump(EXCEPT_ILLEGAL - 4);
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do_jump(EXCEPT_ILLEGAL - 4);
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}
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}
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__or_dynop void op_illegal(void)
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__or_dynop void op_illegal(void)
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{
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{
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env->sprs[SPR_EEAR_BASE] = get_pc();
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env->sprs[SPR_EEAR_BASE] = env->pc;
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do_jump(EXCEPT_ILLEGAL);
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do_jump(EXCEPT_ILLEGAL);
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}
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}
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__or_dynop void op_do_sched(void)
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__or_dynop void op_do_sched(void)
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{
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{
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HANDLE_SCHED(do_sched_wrap, "no_sched");
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SPEEDY_CALL(do_sched_wrap);
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}
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}
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__or_dynop void op_do_sched_delay(void)
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__or_dynop void op_do_sched_delay(void)
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{
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{
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HANDLE_SCHED(do_sched_wrap_delay, "no_sched_delay");
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SPEEDY_CALL(do_sched_wrap_delay);
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}
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}
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__or_dynop void op_macc(void)
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__or_dynop void op_macc(void)
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{
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{
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env->sprs[SPR_MACLO] = 0;
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env->sprs[SPR_MACLO] = 0;
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