| Line 1... |
Line 1... |
/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator
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/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator
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* Copyright (C) 2002 Marko Mlinar, markom@opencores.org
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*
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* This file is part of OpenRISC 1000 Architectural Simulator.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Copyright (C) 2002 Marko Mlinar, markom@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "port.h"
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/* System includes */
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#include <stdio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdarg.h>
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#include <stdarg.h>
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#include <assert.h>
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#include <assert.h>
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#include "config.h"
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/* Package includes */
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#endif
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "cuc.h"
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#include "cuc.h"
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#include "insn.h"
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#include "insn.h"
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#include "profiler.h"
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#include "profiler.h"
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| Line 39... |
Line 45... |
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/* Shortcut */
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/* Shortcut */
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#define GEN(x...) fprintf (fo, x)
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#define GEN(x...) fprintf (fo, x)
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/* Find index of load/store/call */
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/* Find index of load/store/call */
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int find_lsc_index (cuc_func *f, int ref)
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static int
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find_lsc_index (cuc_func * f, int ref)
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{
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{
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int c = 0;
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int c = 0;
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int i;
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int i;
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int load;
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int load;
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if (f->INSN(ref).index == II_CALL) {
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if (f->INSN (ref).index == II_CALL)
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for (i = 0; i < f->nmsched; i++) {
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{
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if (f->msched[i] == ref) break;
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for (i = 0; i < f->nmsched; i++)
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if (f->mtype[i] & MT_CALL) c++;
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{
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if (f->msched[i] == ref)
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break;
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if (f->mtype[i] & MT_CALL)
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c++;
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}
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}
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}
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} else {
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else
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{
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load = II_IS_LOAD (f->INSN(ref).index);
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load = II_IS_LOAD (f->INSN(ref).index);
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for (i = 0; i < f->nmsched; i++) {
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for (i = 0; i < f->nmsched; i++)
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if (f->msched[i] == ref) break;
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{
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if (f->msched[i] == ref)
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break;
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if ((load && (f->mtype[i] & MT_LOAD))
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if ((load && (f->mtype[i] & MT_LOAD))
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|| (!load && (f->mtype[i] & MT_STORE))) c++;
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|| (!load && (f->mtype[i] & MT_STORE)))
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c++;
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}
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}
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}
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}
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return c;
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return c;
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}
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}
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/* Print out dependencies as verilog expression */
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/* Print out dependencies as verilog expression */
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void print_deps (FILE *fo, cuc_func *f, int b, dep_list *t, int registered)
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static void
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print_deps (FILE * fo, cuc_func * f, int b, dep_list * t, int registered)
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{
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if (t)
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{
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{
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if (t) {
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int first = 0;
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int first = 0;
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while (t) {
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while (t)
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if (f->INSN(t->ref).type & IT_MEMORY) {
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{
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if (f->INSN (t->ref).type & IT_MEMORY)
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{
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GEN ("%s%c_end[%i]", first ? " && " : "",
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GEN ("%s%c_end[%i]", first ? " && " : "",
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II_IS_LOAD (f->INSN(t->ref).index) ? 'l' : 's', find_lsc_index (f, t->ref));
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II_IS_LOAD (f->INSN (t->ref).index) ? 'l' : 's',
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} else if (f->INSN(t->ref).index == II_CALL) {
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find_lsc_index (f, t->ref));
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GEN ("%sf_end[%i]", first ? " && " : "", find_lsc_index (f, t->ref));
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}
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} else {
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else if (f->INSN (t->ref).index == II_CALL)
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{
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GEN ("%sf_end[%i]", first ? " && " : "",
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find_lsc_index (f, t->ref));
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}
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else
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{
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PRINTF ("print_deps: err %lx\n", t->ref);
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PRINTF ("print_deps: err %lx\n", t->ref);
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assert (0);
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assert (0);
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}
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}
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first = 1;
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first = 1;
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t = t->next;
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t = t->next;
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}
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}
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} else {
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}
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if (registered) GEN ("bb_start_r[%i]", b);
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else
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else GEN ("bb_start[%i]", b);
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{
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if (registered)
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GEN ("bb_start_r[%i]", b);
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else
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GEN ("bb_start[%i]", b);
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}
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}
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}
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}
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char *print_op_v (cuc_func *f, char *s, int ref, int j)
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static char *
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print_op_v (cuc_func * f, char *s, int ref, int j)
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{
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{
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unsigned long op = f->INSN(ref).op[j];
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unsigned long op = f->INSN(ref).op[j];
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unsigned long opt = f->INSN(ref).opt[j];
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unsigned long opt = f->INSN(ref).opt[j];
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switch (opt & ~OPT_DEST) {
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switch (opt & ~OPT_DEST)
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case OPT_NONE: assert (0); break;
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{
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case OPT_CONST: if (f->INSN(ref).type & IT_COND && (f->INSN(ref).index == II_CMOV
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case OPT_NONE:
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|| f->INSN(ref).index == II_ADD)) {
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assert (0);
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break;
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case OPT_CONST:
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if (f->INSN (ref).type & IT_COND && (f->INSN (ref).index == II_CMOV
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|| f->INSN (ref).index == II_ADD))
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{
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assert (op == 0 || op == 1);
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assert (op == 0 || op == 1);
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sprintf (s, "1'b%lx", op);
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sprintf (s, "1'b%lx", op);
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} else sprintf (s, "32'h%lx", op);
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}
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else
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sprintf (s, "32'h%lx", op);
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break;
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break;
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case OPT_REGISTER:
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case OPT_REGISTER:
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if (opt & OPT_DEST) sprintf (s, "t%x_%x", REF_BB(ref), REF_I(ref));
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if (opt & OPT_DEST)
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else sprintf (s, "r%li_%c", op, opt & OPT_DEST ? 'o' : 'i');
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sprintf (s, "t%x_%x", REF_BB (ref), REF_I (ref));
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else
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sprintf (s, "r%li_%c", op, opt & OPT_DEST ? 'o' : 'i');
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break;
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break;
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#if 0
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#if 0
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case OPT_FREG: assert (opt & OPT_DEST);
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case OPT_FREG:
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assert (opt & OPT_DEST);
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sprintf (s, "fr%i_o", op);
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sprintf (s, "fr%i_o", op);
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break;
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break;
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#endif
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#endif
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case OPT_REF: sprintf (s, "t%lx_%lx", REF_BB(op), REF_I(op)); break;
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case OPT_REF:
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sprintf (s, "t%lx_%lx", REF_BB (op), REF_I (op));
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break;
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}
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}
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return s;
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return s;
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}
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}
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/* Prints out specified instruction */
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/* Prints out specified instruction */
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void print_insn_v (FILE *fo, cuc_func *f, int b, int i)
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static void
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print_insn_v (FILE * fo, cuc_func * f, int b, int i)
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{
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{
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cuc_insn *ii = &f->bb[b].insn[i];
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cuc_insn *ii = &f->bb[b].insn[i];
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char *s = known[ii->index].rtl;
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char *s = known[ii->index].rtl;
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char tmp[200] = "";
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char tmp[200] = "";
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assert (s);
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assert (s);
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while (*s) {
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while (*s)
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if (*s <= MAX_OPERANDS) {
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{
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if (*s <= MAX_OPERANDS)
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{
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char t[30];
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char t[30];
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sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
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sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
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} else if (*s == '\b') sprintf (tmp, "%s%i", tmp, b);
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}
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else sprintf (tmp, "%s%c", tmp, *s);
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else if (*s == '\b')
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sprintf (tmp, "%s%i", tmp, b);
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else
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sprintf (tmp, "%s%c", tmp, *s);
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s++;
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s++;
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}
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}
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GEN ("%-40s /* %s */\n", tmp, ii->disasm);
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GEN ("%-40s /* %s */\n", tmp, ii->disasm);
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if (ii->type & IT_MEMORY) {
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if (ii->type & IT_MEMORY)
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{
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int nls = find_lsc_index (f, REF (b, i));
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int nls = find_lsc_index (f, REF (b, i));
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if (II_IS_LOAD (ii->index)) {
|
if (II_IS_LOAD (ii->index))
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{
|
int nm;
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int nm;
|
for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
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for (nm = 0; nm < f->nmsched; nm++)
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if (f->msched[nm] == REF (b, i))
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break;
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assert (nm < f->nmsched);
|
assert (nm < f->nmsched);
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|
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GEN (" if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
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GEN (" if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
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switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
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switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED))
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case 1: GEN ("l_dat_i & 32'hff;\n");
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{
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case 1:
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GEN ("l_dat_i & 32'hff;\n");
|
break;
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break;
|
case 2: GEN ("l_dat_i & 32'hffff;\n");
|
case 2:
|
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GEN ("l_dat_i & 32'hffff;\n");
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break;
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break;
|
case 4 | MT_SIGNED:
|
case 4 | MT_SIGNED:
|
case 4: GEN ("l_dat_i;\n");
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case 4:
|
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GEN ("l_dat_i;\n");
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break;
|
break;
|
case 1 | MT_SIGNED:
|
case 1 | MT_SIGNED:
|
GEN ("{24{l_dat_i[7]}, l_dat_i[7:0]};\n");
|
GEN ("{24{l_dat_i[7]}, l_dat_i[7:0]};\n");
|
break;
|
break;
|
case 2 | MT_SIGNED:
|
case 2 | MT_SIGNED:
|
GEN ("{16{l_dat_i[15]}, l_dat_i[15:0]};\n");
|
GEN ("{16{l_dat_i[15]}, l_dat_i[15:0]};\n");
|
break;
|
break;
|
default: assert (0);
|
default:
|
|
assert (0);
|
|
}
|
}
|
}
|
}
|
}
|
} else if (ii->index == II_LRBB) {
|
else if (ii->index == II_LRBB)
|
|
{
|
GEN (" if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
|
GEN (" if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
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assert (f->bb[b].prev[0] >= 0);
|
assert (f->bb[b].prev[0] >= 0);
|
if (f->bb[b].prev[0] == BBID_START)
|
if (f->bb[b].prev[0] == BBID_START)
|
GEN (" else if (bb_start[%i]) t%x_%x <= #Tp start_i;\n", b, b, i);
|
GEN (" else if (bb_start[%i]) t%x_%x <= #Tp start_i;\n", b, b, i);
|
else
|
else
|
GEN (" else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
|
GEN (" else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i,
|
} else if (ii->index == II_REG) {
|
f->bb[b].prev[0]);
|
|
}
|
|
else if (ii->index == II_REG)
|
|
{
|
assert (ii->opt[1] == OPT_REF);
|
assert (ii->opt[1] == OPT_REF);
|
GEN (" if (");
|
GEN (" if (");
|
if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
|
if (f->bb[b].mdep)
|
else GEN ("bb_stb[%i]", b);
|
print_deps (fo, f, b, f->bb[b].mdep, 0);
|
|
else
|
|
GEN ("bb_stb[%i]", b);
|
GEN (") t%x_%x <= #Tp t%lx_%lx;\n", b, i,
|
GEN (") t%x_%x <= #Tp t%lx_%lx;\n", b, i,
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REF_BB (ii->op[1]), REF_I (ii->op[1]));
|
REF_BB (ii->op[1]), REF_I (ii->op[1]));
|
}
|
}
|
}
|
}
|
|
|
| Line 183... |
Line 248... |
return bx;
|
return bx;
|
}
|
}
|
*/
|
*/
|
|
|
/* Returns index of branch instruction inside a block b */
|
/* Returns index of branch instruction inside a block b */
|
static int branch_index (cuc_bb *bb)
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static int
|
|
branch_index (cuc_bb * bb)
|
{
|
{
|
int i;
|
int i;
|
for (i = bb->ninsn - 1; i >= 0; i--)
|
for (i = bb->ninsn - 1; i >= 0; i--)
|
if (bb->insn[i].type & IT_BRANCH) return i;
|
if (bb->insn[i].type & IT_BRANCH)
|
|
return i;
|
return -1;
|
return -1;
|
}
|
}
|
|
|
static void print_turn_off_dep (FILE *fo, cuc_func *f, dep_list *dep)
|
static void
|
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print_turn_off_dep (FILE * fo, cuc_func * f, dep_list * dep)
|
|
{
|
|
while (dep)
|
{
|
{
|
while (dep) {
|
assert (f->INSN (dep->ref).type & IT_MEMORY
|
assert (f->INSN(dep->ref).type & IT_MEMORY || f->INSN(dep->ref).index == II_CALL);
|
|| f->INSN (dep->ref).index == II_CALL);
|
GEN (" %c_stb[%i] <= #Tp 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
|
GEN (" %c_stb[%i] <= #Tp 1'b0;\n",
|
: II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_lsc_index (f, dep->ref));
|
f->INSN (dep->ref).index ==
|
|
II_CALL ? 'f' : II_IS_LOAD (f->INSN (dep->ref).index) ? 'l' : 's',
|
|
find_lsc_index (f, dep->ref));
|
dep = dep->next;
|
dep = dep->next;
|
}
|
}
|
}
|
}
|
|
|
static int func_index (cuc_func *f, int ref)
|
static int
|
|
func_index (cuc_func * f, int ref)
|
{
|
{
|
int i;
|
int i;
|
unsigned long addr;
|
unsigned long addr;
|
assert (f->INSN(ref).index == II_CALL && f->INSN(ref).opt[0] & OPT_CONST);
|
assert (f->INSN(ref).index == II_CALL && f->INSN(ref).opt[0] & OPT_CONST);
|
addr = f->INSN(ref).op[0];
|
addr = f->INSN(ref).op[0];
|
for (i = 0; i < f->nfdeps; i++)
|
for (i = 0; i < f->nfdeps; i++)
|
if (f->fdeps[i]->start_addr == addr) return i;
|
if (f->fdeps[i]->start_addr == addr)
|
|
return i;
|
|
|
assert (0);
|
assert (0);
|
return -1;
|
return -1;
|
}
|
}
|
|
|
/* Generates verilog file out of insn dataflow */
|
/* Generates verilog file out of insn dataflow */
|
void output_verilog (cuc_func *f, char *filename, char *funcname)
|
void
|
|
output_verilog (cuc_func * f, char *filename, char *funcname)
|
{
|
{
|
FILE *fo;
|
FILE *fo;
|
int b, i, j;
|
int b, i, j;
|
int ci = 0, co = 0;
|
int ci = 0, co = 0;
|
int nloads = 0, nstores = 0, ncalls = 0;
|
int nloads = 0, nstores = 0, ncalls = 0;
|
char tmp[256];
|
char tmp[256];
|
sprintf (tmp, "%s.v", filename);
|
sprintf (tmp, "%s.v", filename);
|
|
|
log ("Generating verilog file \"%s\"\n", tmp);
|
log ("Generating verilog file \"%s\"\n", tmp);
|
PRINTF ("Generating verilog file \"%s\"\n", tmp);
|
PRINTF ("Generating verilog file \"%s\"\n", tmp);
|
if ((fo = fopen (tmp, "wt+")) == NULL) {
|
if ((fo = fopen (tmp, "wt+")) == NULL)
|
|
{
|
fprintf (stderr, "Cannot open '%s'\n", tmp);
|
fprintf (stderr, "Cannot open '%s'\n", tmp);
|
exit (1);
|
exit (1);
|
}
|
}
|
|
|
/* output header */
|
/* output header */
|
| Line 247... |
Line 323... |
GEN (" s_adr_o, s_dat_o, s_req_o,\n");
|
GEN (" s_adr_o, s_dat_o, s_req_o,\n");
|
GEN (" s_sel_o, s_linbrst_o, s_rdy_i,\n");
|
GEN (" s_sel_o, s_linbrst_o, s_rdy_i,\n");
|
|
|
GEN ("/* inputs */ ");
|
GEN ("/* inputs */ ");
|
for (i = 0; i < MAX_REGS; i++)
|
for (i = 0; i < MAX_REGS; i++)
|
if (f->used_regs[i]) {
|
if (f->used_regs[i])
|
|
{
|
GEN ("r%i_i, ", i);
|
GEN ("r%i_i, ", i);
|
ci++;
|
ci++;
|
}
|
}
|
if (!ci) GEN ("/* NONE */");
|
if (!ci)
|
|
GEN ("/* NONE */");
|
|
|
GEN ("\n/* outputs */ ");
|
GEN ("\n/* outputs */ ");
|
for (i = 0; i < MAX_REGS; i++)
|
for (i = 0; i < MAX_REGS; i++)
|
if (f->lur[i] >= 0 && !f->saved_regs[i]) {
|
if (f->lur[i] >= 0 && !f->saved_regs[i])
|
|
{
|
GEN ("r%i_o, ", i);
|
GEN ("r%i_o, ", i);
|
co++;
|
co++;
|
}
|
}
|
|
|
if (!co) GEN ("/* NONE */");
|
if (!co)
|
if (f->nfdeps) {
|
GEN ("/* NONE */");
|
|
if (f->nfdeps)
|
|
{
|
GEN ("\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
|
GEN ("\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
|
log2_int (f->nfdeps) > 0 ? "fid_o, " : "");
|
log2_int (f->nfdeps) > 0 ? "fid_o, " : "");
|
for (i = 0; i < 6; i++) GEN ("fr%i_o, ", i + 3);
|
for (i = 0; i < 6; i++)
|
|
GEN ("fr%i_o, ", i + 3);
|
}
|
}
|
GEN ("\n start_i, end_o, busy_o);\n\n");
|
GEN ("\n start_i, end_o, busy_o);\n\n");
|
|
|
GEN ("parameter Tp = 1;\n\n");
|
GEN ("parameter Tp = 1;\n\n");
|
|
|
GEN ("input clk, rst;\n");
|
GEN ("input clk, rst;\n");
|
GEN ("input start_i;\t/* Module starts when set to 1 */ \n");
|
GEN ("input start_i;\t/* Module starts when set to 1 */ \n");
|
GEN ("output end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
|
GEN
|
GEN ("output busy_o;\t/* Set when module should not be interrupted */\n");
|
("output end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
|
|
GEN
|
|
("output busy_o;\t/* Set when module should not be interrupted */\n");
|
GEN ("\n/* Bus signals */\n");
|
GEN ("\n/* Bus signals */\n");
|
GEN ("output l_req_o, s_req_o;\n");
|
GEN ("output l_req_o, s_req_o;\n");
|
GEN ("input l_rdy_i, s_rdy_i;\n");
|
GEN ("input l_rdy_i, s_rdy_i;\n");
|
GEN ("output [3:0] l_sel_o, s_sel_o;\n");
|
GEN ("output [3:0] l_sel_o, s_sel_o;\n");
|
GEN ("output [31:0] l_adr_o, s_adr_o;\n");
|
GEN ("output [31:0] l_adr_o, s_adr_o;\n");
|
| Line 289... |
Line 373... |
GEN ("reg [31:0] l_adr_o, s_adr_o;\n");
|
GEN ("reg [31:0] l_adr_o, s_adr_o;\n");
|
GEN ("reg [3:0] l_sel_o, s_sel_o;\n");
|
GEN ("reg [3:0] l_sel_o, s_sel_o;\n");
|
GEN ("reg [31:0] s_dat_o;\n");
|
GEN ("reg [31:0] s_dat_o;\n");
|
GEN ("reg l_linbrst_o, s_linbrst_o;\n");
|
GEN ("reg l_linbrst_o, s_linbrst_o;\n");
|
|
|
if (ci || co) GEN ("\n/* module ports */\n");
|
if (ci || co)
|
if (ci) {
|
GEN ("\n/* module ports */\n");
|
|
if (ci)
|
|
{
|
int first = 1;
|
int first = 1;
|
GEN ("input [31:0]");
|
GEN ("input [31:0]");
|
for (i = 0; i < MAX_REGS; i++)
|
for (i = 0; i < MAX_REGS; i++)
|
if (f->used_regs[i]) {
|
if (f->used_regs[i])
|
|
{
|
GEN ("%sr%i_i", first ? " " : ", ", i);
|
GEN ("%sr%i_i", first ? " " : ", ", i);
|
first = 0;
|
first = 0;
|
}
|
}
|
GEN (";\n");
|
GEN (";\n");
|
}
|
}
|
|
|
if (co) {
|
if (co)
|
|
{
|
int first = 1;
|
int first = 1;
|
GEN ("output [31:0]");
|
GEN ("output [31:0]");
|
for (i = 0; i < MAX_REGS; i++)
|
for (i = 0; i < MAX_REGS; i++)
|
if (f->lur[i] >= 0 && !f->saved_regs[i]) {
|
if (f->lur[i] >= 0 && !f->saved_regs[i])
|
|
{
|
GEN ("%sr%i_o", first ? " " : ", ", i);
|
GEN ("%sr%i_o", first ? " " : ", ", i);
|
first = 0;
|
first = 0;
|
}
|
}
|
GEN (";\n");
|
GEN (";\n");
|
}
|
}
|
|
|
if (f->nfdeps) {
|
if (f->nfdeps)
|
|
{
|
GEN ("\n/* Function calls */\n");
|
GEN ("\n/* Function calls */\n");
|
GEN ("output [31:0] fr3_o");
|
GEN ("output [31:0] fr3_o");
|
for (i = 1; i < 6; i++) GEN (", fr%i_o", i + 3);
|
for (i = 1; i < 6; i++)
|
|
GEN (", fr%i_o", i + 3);
|
GEN (";\n");
|
GEN (";\n");
|
GEN ("input [31:0] fr11_i;\n");
|
GEN ("input [31:0] fr11_i;\n");
|
if (log2_int(f->nfdeps) > 0) GEN ("output [%i:0] fid_o;\n", log2_int(f->nfdeps));
|
if (log2_int (f->nfdeps) > 0)
|
|
GEN ("output [%i:0] fid_o;\n", log2_int (f->nfdeps));
|
GEN ("output fstart_o;\n");
|
GEN ("output fstart_o;\n");
|
GEN ("input fend_i;\n");
|
GEN ("input fend_i;\n");
|
}
|
}
|
|
|
/* Count loads & stores */
|
/* Count loads & stores */
|
for (i = 0; i < f->nmsched; i++)
|
for (i = 0; i < f->nmsched; i++)
|
if (f->mtype[i] & MT_STORE) nstores++;
|
if (f->mtype[i] & MT_STORE)
|
else if (f->mtype[i] & MT_LOAD) nloads++;
|
nstores++;
|
else if (f->mtype[i] & MT_CALL) ncalls++;
|
else if (f->mtype[i] & MT_LOAD)
|
|
nloads++;
|
|
else if (f->mtype[i] & MT_CALL)
|
|
ncalls++;
|
|
|
/* Output internal registers for loads */
|
/* Output internal registers for loads */
|
if (nloads) {
|
if (nloads)
|
|
{
|
int first = 1;
|
int first = 1;
|
int num = 0;
|
int num = 0;
|
GEN ("\n/* internal registers for loads */\n");
|
GEN ("\n/* internal registers for loads */\n");
|
for (i = 0; i < f->nmsched; i++)
|
for (i = 0; i < f->nmsched; i++)
|
if (f->mtype[i] & MT_LOAD) {
|
if (f->mtype[i] & MT_LOAD)
|
|
{
|
GEN ("%st%x_%x", first ? "reg [31:0] " : ", ",
|
GEN ("%st%x_%x", first ? "reg [31:0] " : ", ",
|
REF_BB(f->msched[i]), REF_I(f->msched[i]));
|
REF_BB(f->msched[i]), REF_I(f->msched[i]));
|
|
|
if (num >= 8) {
|
if (num >= 8)
|
|
{
|
GEN (";\n");
|
GEN (";\n");
|
first = 1;
|
first = 1;
|
num = 0;
|
num = 0;
|
} else {
|
}
|
|
else
|
|
{
|
first = 0;
|
first = 0;
|
num++;
|
num++;
|
}
|
}
|
}
|
}
|
if (!first) GEN (";\n");
|
if (!first)
|
|
GEN (";\n");
|
}
|
}
|
|
|
/* Internal register for function return value */
|
/* Internal register for function return value */
|
if (f->nfdeps) {
|
if (f->nfdeps)
|
|
{
|
GEN ("\n/* Internal register for function return value */\n");
|
GEN ("\n/* Internal register for function return value */\n");
|
GEN ("reg [31:0] fr11_r;\n");
|
GEN ("reg [31:0] fr11_r;\n");
|
}
|
}
|
|
|
GEN ("\n/* 'zero or one' hot state machines */\n");
|
GEN ("\n/* 'zero or one' hot state machines */\n");
|
if (nloads) GEN ("reg [%i:0] l_stb; /* loads */\n", nloads - 1);
|
if (nloads)
|
if (nstores) GEN ("reg [%i:0] s_stb; /* stores */\n", nstores - 1);
|
GEN ("reg [%i:0] l_stb; /* loads */\n", nloads - 1);
|
|
if (nstores)
|
|
GEN ("reg [%i:0] s_stb; /* stores */\n", nstores - 1);
|
GEN ("reg [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
|
GEN ("reg [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
|
|
|
{
|
{
|
int first = 2;
|
int first = 2;
|
int num = 0;
|
int num = 0;
|
for (b = 0; b < f->num_bb; b++)
|
for (b = 0; b < f->num_bb; b++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
if (f->bb[b].insn[i].type & IT_COND
|
if (f->bb[b].insn[i].type & IT_COND
|
&& f->bb[b].insn[i].index != II_REG
|
&& f->bb[b].insn[i].index != II_REG
|
&& f->bb[b].insn[i].index != II_LRBB) {
|
&& f->bb[b].insn[i].index != II_LRBB)
|
if (first == 2) GEN ("\n/* basic block condition wires */\n");
|
{
|
|
if (first == 2)
|
|
GEN ("\n/* basic block condition wires */\n");
|
GEN ("%st%x_%x", first ? "wire " : ", ", b, i);
|
GEN ("%st%x_%x", first ? "wire " : ", ", b, i);
|
if (num >= 8) {
|
if (num >= 8)
|
|
{
|
GEN (";\n");
|
GEN (";\n");
|
first = 1;
|
first = 1;
|
num = 0;
|
num = 0;
|
} else {
|
}
|
|
else
|
|
{
|
first = 0;
|
first = 0;
|
num++;
|
num++;
|
}
|
}
|
}
|
}
|
if (!first) GEN (";\n");
|
if (!first)
|
|
GEN (";\n");
|
|
|
GEN ("\n/* forward declaration of normal wires */\n");
|
GEN ("\n/* forward declaration of normal wires */\n");
|
num = 0;
|
num = 0;
|
first = 1;
|
first = 1;
|
for (b = 0; b < f->num_bb; b++)
|
for (b = 0; b < f->num_bb; b++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))
|
if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))
|
&& f->bb[b].insn[i].index != II_REG
|
&& f->bb[b].insn[i].index != II_REG
|
&& f->bb[b].insn[i].index != II_LRBB) {
|
&& f->bb[b].insn[i].index != II_LRBB)
|
|
{
|
/* Exclude loads */
|
/* Exclude loads */
|
if (f->bb[b].insn[i].type & IT_MEMORY && II_IS_LOAD (f->bb[b].insn[i].index)) continue;
|
if (f->bb[b].insn[i].type & IT_MEMORY
|
|
&& II_IS_LOAD (f->bb[b].insn[i].index))
|
|
continue;
|
GEN ("%st%x_%x", first ? "wire [31:0] " : ", ", b, i);
|
GEN ("%st%x_%x", first ? "wire [31:0] " : ", ", b, i);
|
if (num >= 8) {
|
if (num >= 8)
|
|
{
|
GEN (";\n");
|
GEN (";\n");
|
first = 1;
|
first = 1;
|
num = 0;
|
num = 0;
|
} else {
|
}
|
|
else
|
|
{
|
first = 0;
|
first = 0;
|
num++;
|
num++;
|
}
|
}
|
}
|
}
|
if (!first) GEN (";\n");
|
if (!first)
|
|
GEN (";\n");
|
|
|
GEN ("\n/* forward declaration registers */\n");
|
GEN ("\n/* forward declaration registers */\n");
|
num = 0;
|
num = 0;
|
first = 1;
|
first = 1;
|
for (b = 0; b < f->num_bb; b++)
|
for (b = 0; b < f->num_bb; b++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
if (f->bb[b].insn[i].index == II_REG
|
if (f->bb[b].insn[i].index == II_REG
|
&& f->bb[b].insn[i].index != II_LRBB) {
|
&& f->bb[b].insn[i].index != II_LRBB)
|
|
{
|
GEN ("%st%x_%x", first ? "reg [31:0] " : ", ", b, i);
|
GEN ("%st%x_%x", first ? "reg [31:0] " : ", ", b, i);
|
if (num >= 8) {
|
if (num >= 8)
|
|
{
|
GEN (";\n");
|
GEN (";\n");
|
first = 1;
|
first = 1;
|
num = 0;
|
num = 0;
|
} else {
|
}
|
|
else
|
|
{
|
first = 0;
|
first = 0;
|
num++;
|
num++;
|
}
|
}
|
}
|
}
|
if (!first) GEN (";\n");
|
if (!first)
|
|
GEN (";\n");
|
|
|
num = 0;
|
num = 0;
|
first = 1;
|
first = 1;
|
for (b = 0; b < f->num_bb; b++)
|
for (b = 0; b < f->num_bb; b++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
if (f->bb[b].insn[i].index != II_REG
|
if (f->bb[b].insn[i].index != II_REG
|
&& f->bb[b].insn[i].index == II_LRBB) {
|
&& f->bb[b].insn[i].index == II_LRBB)
|
|
{
|
GEN ("%st%x_%x", first ? "reg " : ", ", b, i);
|
GEN ("%st%x_%x", first ? "reg " : ", ", b, i);
|
if (num >= 8) {
|
if (num >= 8)
|
|
{
|
GEN (";\n");
|
GEN (";\n");
|
first = 1;
|
first = 1;
|
num = 0;
|
num = 0;
|
} else {
|
}
|
|
else
|
|
{
|
first = 0;
|
first = 0;
|
num++;
|
num++;
|
}
|
}
|
}
|
}
|
if (!first) GEN (";\n");
|
if (!first)
|
|
GEN (";\n");
|
}
|
}
|
|
|
if (nloads || nstores) GEN ("\n/* dependencies */\n");
|
if (nloads || nstores)
|
if (nloads) GEN ("wire [%i:0] l_end = l_stb & {%i{l_rdy_i}};\n",
|
GEN ("\n/* dependencies */\n");
|
|
if (nloads)
|
|
GEN ("wire [%i:0] l_end = l_stb & {%i{l_rdy_i}};\n",
|
nloads - 1, nloads);
|
nloads - 1, nloads);
|
if (nstores) GEN ("wire [%i:0] s_end = s_stb & {%i{s_rdy_i}};\n",
|
if (nstores)
|
|
GEN ("wire [%i:0] s_end = s_stb & {%i{s_rdy_i}};\n",
|
nstores - 1, nstores);
|
nstores - 1, nstores);
|
if (ncalls) GEN ("wire [%i:0] f_end = f_stb & {%i{fend_i}};\n",
|
if (ncalls)
|
|
GEN ("wire [%i:0] f_end = f_stb & {%i{fend_i}};\n",
|
ncalls - 1, ncalls);
|
ncalls - 1, ncalls);
|
|
|
GEN ("\n/* last dependency */\n");
|
GEN ("\n/* last dependency */\n");
|
GEN ("wire end_o = ");
|
GEN ("wire end_o = ");
|
for (b = 0; b < f->num_bb; b++) {
|
for (b = 0; b < f->num_bb; b++)
|
for (i = 0; i < 2; i++) if (f->bb[b].next[i] == BBID_END) {
|
{
|
|
for (i = 0; i < 2; i++)
|
|
if (f->bb[b].next[i] == BBID_END)
|
|
{
|
GEN ("bb_stb[%i]", b);
|
GEN ("bb_stb[%i]", b);
|
if (f->bb[b].mdep) {
|
if (f->bb[b].mdep)
|
|
{
|
GEN (" && ");
|
GEN (" && ");
|
print_deps (fo, f, b, f->bb[b].mdep, 0);
|
print_deps (fo, f, b, f->bb[b].mdep, 0);
|
}
|
}
|
/* Is branch to BBID_END conditional? */
|
/* Is branch to BBID_END conditional? */
|
if (f->bb[b].next[1 - i] >= 0) {
|
if (f->bb[b].next[1 - i] >= 0)
|
|
{
|
int bidx = branch_index (&f->bb[b]);
|
int bidx = branch_index (&f->bb[b]);
|
char t[30];
|
char t[30];
|
print_op_v (f, t, REF (b, bidx), 1);
|
print_op_v (f, t, REF (b, bidx), 1);
|
GEN (" && %s%s", i ? "" : "!", t);
|
GEN (" && %s%s", i ? "" : "!", t);
|
}
|
}
|
| Line 475... |
Line 611... |
GEN ("wire busy_o = |bb_stb;\n");
|
GEN ("wire busy_o = |bb_stb;\n");
|
|
|
|
|
GEN ("\n/* Basic block triggers */\n");
|
GEN ("\n/* Basic block triggers */\n");
|
GEN ("wire [%2i:0] bb_start = {\n", f->num_bb - 1);
|
GEN ("wire [%2i:0] bb_start = {\n", f->num_bb - 1);
|
for (b = f->num_bb - 1; b >= 0; b--) {
|
for (b = f->num_bb - 1; b >= 0; b--)
|
|
{
|
GEN (" /* bb_start[%2i] */ ", b);
|
GEN (" /* bb_start[%2i] */ ", b);
|
for (i = 0; i < 2; i++) if (f->bb[b].prev[i] >= 0 && f->bb[b].prev[i] != BBID_START) {
|
for (i = 0; i < 2; i++)
|
|
if (f->bb[b].prev[i] >= 0 && f->bb[b].prev[i] != BBID_START)
|
|
{
|
cuc_bb *prev = &f->bb[f->bb[b].prev[i]];
|
cuc_bb *prev = &f->bb[f->bb[b].prev[i]];
|
int t;
|
int t;
|
if (i) GEN ("\n || ");
|
if (i)
|
if (prev->mdep) {
|
GEN ("\n || ");
|
|
if (prev->mdep)
|
|
{
|
print_deps (fo, f, f->bb[b].prev[i], prev->mdep, 0);
|
print_deps (fo, f, f->bb[b].prev[i], prev->mdep, 0);
|
GEN (" && ");
|
GEN (" && ");
|
}
|
}
|
GEN ("bb_stb[%i]", f->bb[b].prev[i]);
|
GEN ("bb_stb[%i]", f->bb[b].prev[i]);
|
if (prev->next[0] >= 0 && prev->next[0] != BBID_END
|
if (prev->next[0] >= 0 && prev->next[0] != BBID_END
|
&& prev->next[1] >= 0 && prev->next[1] != BBID_END) {
|
&& prev->next[1] >= 0 && prev->next[1] != BBID_END)
|
int bi = REF (f->bb[b].prev[i], branch_index (&f->bb[f->bb[b].prev[i]]));
|
{
|
|
int bi =
|
|
REF (f->bb[b].prev[i],
|
|
branch_index (&f->bb[f->bb[b].prev[i]]));
|
int ci;
|
int ci;
|
assert (bi >= 0);
|
assert (bi >= 0);
|
ci = f->INSN(bi).op[1];
|
ci = f->INSN(bi).op[1];
|
t = prev->next[0] == b;
|
t = prev->next[0] == b;
|
GEN (" && ");
|
GEN (" && ");
|
if (f->INSN(bi).opt[1] & OPT_REF) {
|
if (f->INSN (bi).opt[1] & OPT_REF)
|
|
{
|
GEN ("%st%x_%x", t ? "" : "!", REF_BB(ci), REF_I(ci));
|
GEN ("%st%x_%x", t ? "" : "!", REF_BB(ci), REF_I(ci));
|
} else {
|
}
|
|
else
|
|
{
|
cucdebug (5, "%x!%x!%x\n", bi, ci, f->INSN(bi).opt[1]);
|
cucdebug (5, "%x!%x!%x\n", bi, ci, f->INSN(bi).opt[1]);
|
assert (f->INSN(bi).opt[1] & OPT_CONST);
|
assert (f->INSN(bi).opt[1] & OPT_CONST);
|
GEN ("%s%i", t ? "" : "!", ci);
|
GEN ("%s%i", t ? "" : "!", ci);
|
}
|
}
|
}
|
}
|
} else break;
|
}
|
if (!i) GEN ("start_i");
|
else
|
if (b == 0) GEN ("};\n");
|
break;
|
else GEN (",\n");
|
if (!i)
|
|
GEN ("start_i");
|
|
if (b == 0)
|
|
GEN ("};\n");
|
|
else
|
|
GEN (",\n");
|
}
|
}
|
|
|
GEN ("\n/* Register the bb_start */\n");
|
GEN ("\n/* Register the bb_start */\n");
|
GEN ("reg [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
|
GEN ("reg [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
|
GEN ("always @(posedge rst or posedge clk)\n");
|
GEN ("always @(posedge rst or posedge clk)\n");
|
| Line 519... |
Line 671... |
GEN (" else bb_start_r <= #Tp bb_start;\n");
|
GEN (" else bb_start_r <= #Tp bb_start;\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
|
|
GEN ("\n/* Logic */\n");
|
GEN ("\n/* Logic */\n");
|
/* output body */
|
/* output body */
|
for (b = 0; b < f->num_bb; b++) {
|
for (b = 0; b < f->num_bb; b++)
|
|
{
|
GEN ("\t\t/* BB%i */\n", b);
|
GEN ("\t\t/* BB%i */\n", b);
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
print_insn_v (fo, f, b, i);
|
print_insn_v (fo, f, b, i);
|
GEN ("\n");
|
GEN ("\n");
|
}
|
}
|
|
|
if (co) {
|
if (co)
|
|
{
|
GEN ("\n/* Outputs */\n");
|
GEN ("\n/* Outputs */\n");
|
for (i = 0; i < MAX_REGS; i++)
|
for (i = 0; i < MAX_REGS; i++)
|
if (f->lur[i] >= 0 && !f->saved_regs[i])
|
if (f->lur[i] >= 0 && !f->saved_regs[i])
|
GEN ("assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
|
GEN ("assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
|
REF_I(f->lur[i]));
|
REF_I(f->lur[i]));
|
}
|
}
|
|
|
if (nstores) {
|
if (nstores)
|
|
{
|
int cur_store;
|
int cur_store;
|
GEN ("\n/* Memory stores */\n");
|
GEN ("\n/* Memory stores */\n");
|
GEN ("always @(s_stb");
|
GEN ("always @(s_stb");
|
for (i = 0; i < f->nmsched; i++)
|
for (i = 0; i < f->nmsched; i++)
|
if (f->mtype[i] & MT_STORE) {
|
if (f->mtype[i] & MT_STORE)
|
|
{
|
char t[30];
|
char t[30];
|
unsigned long opt = f->INSN(f->msched[i]).opt[0];
|
unsigned long opt = f->INSN(f->msched[i]).opt[0];
|
if ((opt & ~OPT_DEST) != OPT_CONST) {
|
if ((opt & ~OPT_DEST) != OPT_CONST)
|
|
{
|
GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
|
GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
|
}
|
}
|
}
|
}
|
|
|
cur_store = 0;
|
cur_store = 0;
|
GEN (")\nbegin\n");
|
GEN (")\nbegin\n");
|
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
|
for (i = 0; i < f->nmsched; i++)
|
|
if (f->mtype[i] & MT_STORE)
|
|
{
|
char t[30];
|
char t[30];
|
GEN (" %sif (s_stb[%i]) s_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
|
GEN (" %sif (s_stb[%i]) s_dat_o = %s;\n",
|
print_op_v (f, t, f->msched[i], 0));
|
cur_store == 0 ? "" : "else ", cur_store, print_op_v (f, t,
|
|
f->
|
|
msched
|
|
[i],
|
|
0));
|
cur_store++;
|
cur_store++;
|
//PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
|
//PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
|
}
|
}
|
GEN (" else s_dat_o = 32'hx;\n");
|
GEN (" else s_dat_o = 32'hx;\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
| Line 565... |
Line 728... |
/* Generate load and store state machine */
|
/* Generate load and store state machine */
|
#if 0
|
#if 0
|
GEN ("\n/* Load&store state machine */\n");
|
GEN ("\n/* Load&store state machine */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) begin\n");
|
GEN (" if (rst) begin\n");
|
if (nloads) GEN (" l_stb <= #Tp %i'h0;\n", nloads);
|
if (nloads)
|
if (nstores) GEN (" s_stb <= #Tp %i'h0;\n", nstores);
|
GEN (" l_stb <= #Tp %i'h0;\n", nloads);
|
|
if (nstores)
|
|
GEN (" s_stb <= #Tp %i'h0;\n", nstores);
|
GEN (" end else begin\n");
|
GEN (" end else begin\n");
|
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) {
|
for (i = 0; i < f->nmsched; i++)
|
|
if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE)
|
|
{
|
int cur = 0;
|
int cur = 0;
|
dep_list *dep = f->INSN(f->msched[i]).dep;
|
dep_list *dep = f->INSN(f->msched[i]).dep;
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
GEN (" if (");
|
GEN (" if (");
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
print_deps (fo, f, REF_BB (f->msched[i]), f->INSN (f->msched[i]).dep,
|
|
1);
|
GEN (") begin\n");
|
GEN (") begin\n");
|
print_turn_off_dep (fo, f, dep);
|
print_turn_off_dep (fo, f, dep);
|
GEN (" %c_stb[%i] <= #Tp 1'b1;\n", f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
|
GEN (" %c_stb[%i] <= #Tp 1'b1;\n",
|
|
f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
|
GEN (" end\n");
|
GEN (" end\n");
|
}
|
}
|
GEN (" if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
|
GEN (" if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
|
GEN (" end\n");
|
GEN (" end\n");
|
#endif
|
#endif
|
|
|
/* Generate state generator machine */
|
/* Generate state generator machine */
|
for (j = 0; j < 2; j++) {
|
for (j = 0; j < 2; j++)
|
|
{
|
char c;
|
char c;
|
char *s;
|
char *s;
|
|
|
switch (j) {
|
switch (j)
|
case 0: c = 'l'; s = "Load"; break;
|
{
|
case 1: c = 's'; s = "Store"; break;
|
case 0:
|
case 2: c = 'c'; s = "Calls"; break;
|
c = 'l';
|
}
|
s = "Load";
|
if ((j == 0 && nloads)
|
break;
|
|| (j == 1 && nstores)
|
case 1:
|
|| (j == 2 && ncalls)) {
|
c = 's';
|
|
s = "Store";
|
|
break;
|
|
case 2:
|
|
c = 'c';
|
|
s = "Calls";
|
|
break;
|
|
}
|
|
if ((j == 0 && nloads) || (j == 1 && nstores) || (j == 2 && ncalls))
|
|
{
|
int cur = 0;
|
int cur = 0;
|
char t[30];
|
char t[30];
|
|
|
GEN ("\n/* %s state generator machine */\n", s);
|
GEN ("\n/* %s state generator machine */\n", s);
|
GEN ("always @(");
|
GEN ("always @(");
|
for (i = 0; i < f->nmsched; i++) {
|
for (i = 0; i < f->nmsched; i++)
|
|
{
|
print_op_v (f, t, f->msched[i], 1);
|
print_op_v (f, t, f->msched[i], 1);
|
GEN ("%s or ", t);
|
GEN ("%s or ", t);
|
}
|
}
|
GEN ("bb_start_r");
|
GEN ("bb_start_r");
|
if (nloads) GEN (" or l_end");
|
if (nloads)
|
if (nstores) GEN (" or s_end");
|
GEN (" or l_end");
|
|
if (nstores)
|
|
GEN (" or s_end");
|
GEN (")\n");
|
GEN (")\n");
|
GEN ("begin\n ");
|
GEN ("begin\n ");
|
cucdebug (1, "%s\n", s);
|
cucdebug (1, "%s\n", s);
|
for (i = 0; i < f->nmsched; i++)
|
for (i = 0; i < f->nmsched; i++)
|
if ((j == 0 && f->mtype[i] & MT_LOAD)
|
if ((j == 0 && f->mtype[i] & MT_LOAD)
|
|| (j == 1 && f->mtype[i] & MT_STORE)
|
|| (j == 1 && f->mtype[i] & MT_STORE)
|
|| (j == 2 && f->mtype[i] & MT_CALL)) {
|
|| (j == 2 && f->mtype[i] & MT_CALL))
|
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
{
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i],
|
|
f->mtype[i]);
|
|
assert (f->INSN (f->msched[i]).
|
|
opt[1] & (OPT_REF | OPT_REGISTER));
|
GEN ("if (");
|
GEN ("if (");
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
print_deps (fo, f, REF_BB (f->msched[i]),
|
|
f->INSN (f->msched[i]).dep, 1);
|
GEN (") begin\n");
|
GEN (") begin\n");
|
GEN (" %c_req_o = 1'b1;\n", c);
|
GEN (" %c_req_o = 1'b1;\n", c);
|
GEN (" %c_sel_o[3:0] = 4'b", c);
|
GEN (" %c_sel_o[3:0] = 4'b", c);
|
switch (f->mtype[i] & MT_WIDTH) {
|
switch (f->mtype[i] & MT_WIDTH)
|
case 1: GEN ("0001 << (%s & 32'h3);\n",
|
{
|
print_op_v (f, t, f->msched[i], 1)); break;
|
case 1:
|
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
|
GEN ("0001 << (%s & 32'h3);\n",
|
print_op_v (f, t, f->msched[i], 1)); break;
|
print_op_v (f, t, f->msched[i], 1));
|
case 4: GEN ("1111;\n"); break;
|
break;
|
default: assert (0);
|
case 2:
|
|
GEN ("0011 << ((%s & 32'h1) << 1);\n",
|
|
print_op_v (f, t, f->msched[i], 1));
|
|
break;
|
|
case 4:
|
|
GEN ("1111;\n");
|
|
break;
|
|
default:
|
|
assert (0);
|
}
|
}
|
GEN (" %c_linbrst_o = 1'b%i;\n", c,
|
GEN (" %c_linbrst_o = 1'b%i;\n", c,
|
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
|
(f->mtype[i] & MT_BURST)
|
|
&& !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
|
GEN (" %c_adr_o = t%lx_%lx & ~32'h3;\n", c,
|
GEN (" %c_adr_o = t%lx_%lx & ~32'h3;\n", c,
|
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
|
REF_BB (f->INSN (f->msched[i]).op[1]),
|
|
REF_I (f->INSN (f->msched[i]).op[1]));
|
GEN (" end else ");
|
GEN (" end else ");
|
}
|
}
|
GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
|
GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
|
GEN (" %c_req_o = 1'b0;\n", c);
|
GEN (" %c_req_o = 1'b0;\n", c);
|
GEN (" %c_sel_o[3:0] = 4'bx;\n", c);
|
GEN (" %c_sel_o[3:0] = 4'bx;\n", c);
|
| Line 651... |
Line 847... |
GEN (" end\n");
|
GEN (" end\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
}
|
}
|
|
|
if (ncalls) {
|
if (ncalls)
|
|
{
|
int cur_call = 0;
|
int cur_call = 0;
|
GEN ("\n/* Function calls state machine */\n");
|
GEN ("\n/* Function calls state machine */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) begin\n");
|
GEN (" if (rst) begin\n");
|
GEN (" f_stb <= #Tp %i'h0;\n", nstores);
|
GEN (" f_stb <= #Tp %i'h0;\n", nstores);
|
for (i = 0; i < 6; i++) GEN (" fr%i_o <= #Tp 32'h0;\n", i + 3);
|
for (i = 0; i < 6; i++)
|
if (log2_int(ncalls)) GEN (" fid_o <= #Tp %i'h0;\n", log2_int (f->nfdeps));
|
GEN (" fr%i_o <= #Tp 32'h0;\n", i + 3);
|
|
if (log2_int (ncalls))
|
|
GEN (" fid_o <= #Tp %i'h0;\n", log2_int (f->nfdeps));
|
GEN (" fstart_o <= #Tp 1'b0;\n");
|
GEN (" fstart_o <= #Tp 1'b0;\n");
|
//GEN (" f11_r <= #Tp 32'h0;\n");
|
//GEN (" f11_r <= #Tp 32'h0;\n");
|
GEN (" end else begin\n");
|
GEN (" end else begin\n");
|
cucdebug (1, "calls \n");
|
cucdebug (1, "calls \n");
|
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_CALL) {
|
for (i = 0; i < f->nmsched; i++)
|
|
if (f->mtype[i] & MT_CALL)
|
|
{
|
dep_list *dep = f->INSN(f->msched[i]).dep;
|
dep_list *dep = f->INSN(f->msched[i]).dep;
|
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i],
|
|
f->mtype[i]);
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
GEN (" if (");
|
GEN (" if (");
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
print_deps (fo, f, REF_BB (f->msched[i]),
|
|
f->INSN (f->msched[i]).dep, 1);
|
GEN (") begin\n");
|
GEN (") begin\n");
|
print_turn_off_dep (fo, f, dep);
|
print_turn_off_dep (fo, f, dep);
|
GEN (" f_stb[%i] <= #Tp 1'b1;\n", cur_call++);
|
GEN (" f_stb[%i] <= #Tp 1'b1;\n", cur_call++);
|
GEN (" fstart_o <= #Tp 1'b1;\n");
|
GEN (" fstart_o <= #Tp 1'b1;\n");
|
if (log2_int (f->nfdeps))
|
if (log2_int (f->nfdeps))
|
GEN (" fid_o <= #Tp %i'h%x;\n", log2_int (f->nfdeps), func_index (f, f->msched[i]));
|
GEN (" fid_o <= #Tp %i'h%x;\n", log2_int (f->nfdeps),
|
|
func_index (f, f->msched[i]));
|
|
|
for (j = 0; j < 6; j++)
|
for (j = 0; j < 6; j++)
|
GEN (" fr%i_o <= #Tp t%x_%x;\n", j + 3,
|
GEN (" fr%i_o <= #Tp t%x_%x;\n", j + 3,
|
REF_BB (f->msched[i]), REF_I (f->msched[i]) - 6 + i);
|
REF_BB (f->msched[i]), REF_I (f->msched[i]) - 6 + i);
|
GEN (" end\n");
|
GEN (" end\n");
|
| Line 696... |
Line 900... |
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" else if (end_o) begin\n");
|
GEN (" else if (end_o) begin\n");
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
for (i = 0; i < f->num_bb; i++) {
|
for (i = 0; i < f->num_bb; i++)
|
|
{
|
GEN (" end else if (bb_start[%i]) begin\n", i);
|
GEN (" end else if (bb_start[%i]) begin\n", i);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
|
}
|
}
|
GEN (" end else if (end_o) begin\n");
|
GEN (" end else if (end_o) begin\n");
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
| Line 711... |
Line 916... |
GEN ("\nendmodule\n");
|
GEN ("\nendmodule\n");
|
|
|
fclose (fo);
|
fclose (fo);
|
}
|
}
|
|
|
void generate_main (int nfuncs, cuc_func **f, char *filename)
|
void
|
|
generate_main (int nfuncs, cuc_func ** f, char *filename)
|
{
|
{
|
FILE *fo;
|
FILE *fo;
|
int i, j, nrf, first;
|
int i, j, nrf, first;
|
char tmp[256];
|
char tmp[256];
|
int ncallees[MAX_FUNCS];
|
int ncallees[MAX_FUNCS];
|
int nl[MAX_FUNCS], ns[MAX_FUNCS];
|
int nl[MAX_FUNCS], ns[MAX_FUNCS];
|
int maxncallees = 0;
|
int maxncallees = 0;
|
sprintf (tmp, "%s_top.v", filename);
|
sprintf (tmp, "%s_top.v", filename);
|
|
|
for (i = 0, nrf = 0; i < nfuncs; i++) {
|
for (i = 0, nrf = 0; i < nfuncs; i++)
|
|
{
|
nl[i] = ns[i] = 0;
|
nl[i] = ns[i] = 0;
|
ncallees[i] = 0;
|
ncallees[i] = 0;
|
if (f[i]) {
|
if (f[i])
|
|
{
|
f[i]->tmp = nrf++;
|
f[i]->tmp = nrf++;
|
for (j = 0; j < f[i]->nmsched; j++)
|
for (j = 0; j < f[i]->nmsched; j++)
|
if (f[i]->mtype[j] & MT_LOAD) nl[i]++;
|
if (f[i]->mtype[j] & MT_LOAD)
|
else if (f[i]->mtype[j] & MT_STORE) ns[i]++;
|
nl[i]++;
|
|
else if (f[i]->mtype[j] & MT_STORE)
|
|
ns[i]++;
|
for (j = 0; j < f[i]->nfdeps; j++)
|
for (j = 0; j < f[i]->nfdeps; j++)
|
ncallees[f[i]->fdeps[j]->tmp]++;
|
ncallees[f[i]->fdeps[j]->tmp]++;
|
}
|
}
|
}
|
}
|
if (!nrf) return;
|
if (!nrf)
|
|
return;
|
|
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++)
|
if (maxncallees < ncallees[i]) maxncallees = ncallees[i];
|
if (maxncallees < ncallees[i])
|
|
maxncallees = ncallees[i];
|
|
|
log ("Generating verilog file \"%s\"\n", tmp);
|
log ("Generating verilog file \"%s\"\n", tmp);
|
PRINTF ("Generating verilog file \"%s\"\n", tmp);
|
PRINTF ("Generating verilog file \"%s\"\n", tmp);
|
if ((fo = fopen (tmp, "wt+")) == NULL) {
|
if ((fo = fopen (tmp, "wt+")) == NULL)
|
|
{
|
fprintf (stderr, "Cannot open '%s'\n", tmp);
|
fprintf (stderr, "Cannot open '%s'\n", tmp);
|
exit (1);
|
exit (1);
|
}
|
}
|
|
|
/* output header */
|
/* output header */
|
GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
|
GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
|
GEN (" (C) 2002 Opencores */\n\n");
|
GEN (" (C) 2002 Opencores */\n\n");
|
GEN ("/* Includes %i functions:", nrf);
|
GEN ("/* Includes %i functions:", nrf);
|
for (i = 0; i < nfuncs; i++) if (f[i])
|
for (i = 0; i < nfuncs; i++)
|
|
if (f[i])
|
GEN ("\n%s", prof_func[i].name);
|
GEN ("\n%s", prof_func[i].name);
|
GEN (" */\n\n");
|
GEN (" */\n\n");
|
|
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN ("module %s (clk, rst,\n", filename);
|
| Line 761... |
Line 975... |
GEN (" l_adr_o, l_dat_i, l_cyc_o, l_stb_o,\n");
|
GEN (" l_adr_o, l_dat_i, l_cyc_o, l_stb_o,\n");
|
GEN (" l_sel_o, l_linbrst_o, l_rdy_i, l_we_o,\n");
|
GEN (" l_sel_o, l_linbrst_o, l_rdy_i, l_we_o,\n");
|
GEN (" s_adr_o, s_dat_o, s_cyc_o, s_stb_o,\n");
|
GEN (" s_adr_o, s_dat_o, s_cyc_o, s_stb_o,\n");
|
GEN (" s_sel_o, s_linbrst_o, s_rdy_i, s_we_o,\n\n");
|
GEN (" s_sel_o, s_linbrst_o, s_rdy_i, s_we_o,\n\n");
|
GEN (" /* cuc interface */\n");
|
GEN (" /* cuc interface */\n");
|
GEN (" cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_rdy_o);\n\n");
|
GEN
|
|
(" cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_rdy_o);\n\n");
|
|
|
GEN ("parameter Tp = 1;\n");
|
GEN ("parameter Tp = 1;\n");
|
GEN ("\n/* module ports */\n");
|
GEN ("\n/* module ports */\n");
|
GEN ("input clk, rst, cuc_stb_i, cuc_we_i;\n");
|
GEN ("input clk, rst, cuc_stb_i, cuc_we_i;\n");
|
GEN ("input l_rdy_i, s_rdy_i;\n");
|
GEN ("input l_rdy_i, s_rdy_i;\n");
|
| Line 779... |
Line 994... |
GEN ("output [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
|
GEN ("output [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
|
GEN ("reg [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
|
GEN ("reg [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
|
GEN ("input [15:0] cuc_adr_i;\n");
|
GEN ("input [15:0] cuc_adr_i;\n");
|
GEN ("input [31:0] l_dat_i, cuc_dat_i;\n\n");
|
GEN ("input [31:0] l_dat_i, cuc_dat_i;\n\n");
|
|
|
GEN ("wire [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n",
|
GEN ("wire [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n", nrf - 1);
|
nrf - 1);
|
|
GEN
|
|
("wire [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n",
|
|
nrf - 1);
|
GEN ("wire [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_l_req, i_s_req;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_l_req, i_s_req;\n", nrf - 1);
|
GEN ("reg [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
|
GEN ("reg [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
|
|
|
GEN ("assign i_selected = {\n");
|
GEN ("assign i_selected = {\n");
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++)
|
GEN (" cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
|
GEN (" cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
|
|
|
GEN ("assign i_first_reg = {\n");
|
GEN ("assign i_first_reg = {\n");
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++)
|
for (j = 0; j <= MAX_REGS; j++) if (f[i]->used_regs[j]) break;
|
if (f[i])
|
GEN (" cuc_adr_i[5:0] == %i%s\n", j, f[i]->tmp < nrf - 1 ? "," : "};");
|
{
|
|
for (j = 0; j <= MAX_REGS; j++)
|
|
if (f[i]->used_regs[j])
|
|
break;
|
|
GEN (" cuc_adr_i[5:0] == %i%s\n", j,
|
|
f[i]->tmp < nrf - 1 ? "," : "};");
|
}
|
}
|
|
|
GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
|
GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
|
GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
|
GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
|
|
|
GEN ("assign i_start = i_go_bsy & {%i{cuc_rdy_o}};\n", nrf);
|
GEN ("assign i_start = i_go_bsy & {%i{cuc_rdy_o}};\n", nrf);
|
GEN ("assign i_start_bidok = {\n");
|
GEN ("assign i_start_bidok = {\n");
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++)
|
GEN (" i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
|
GEN (" i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
|
GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
|
GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
|
GEN ("assign main_end = {%i{i_end}} & i_selected;\n");
|
GEN ("assign main_end = {%i{i_end}} & i_selected;\n",
|
|
nrf - 1); /* JPB guess at missing args */
|
|
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
|
GEN (" if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
|
GEN (" else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
|
GEN (" else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
|
|
|
|
/* Function specific data */
|
/* Function specific data */
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++)
|
|
if (f[i])
|
|
{
|
int ci = 0, co = 0;
|
int ci = 0, co = 0;
|
int fn = f[i]->tmp;
|
int fn = f[i]->tmp;
|
GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
|
GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j]) {
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
GEN ("%s i%i_r%ii", first ? "/* inputs */\nreg [31:0]" : ",", fn, j);
|
if (f[i]->used_regs[j])
|
|
{
|
|
GEN ("%s i%i_r%ii", first ? "/* inputs */\nreg [31:0]" : ",",
|
|
fn, j);
|
first = 0;
|
first = 0;
|
ci++;
|
ci++;
|
}
|
}
|
if (ci) GEN (";\n");
|
if (ci)
|
|
GEN (";\n");
|
|
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
GEN ("%s i%i_r%io", first ? "/* outputs */\nwire [31:0]" : ",", fn, j);
|
{
|
|
GEN ("%s i%i_r%io",
|
|
first ? "/* outputs */\nwire [31:0]" : ",", fn, j);
|
first = 0;
|
first = 0;
|
co++;
|
co++;
|
}
|
}
|
if (co) GEN (";\n");
|
if (co)
|
|
GEN (";\n");
|
GEN ("wire [31:0] i%i_l_adr, i%i_s_adr;\n", fn, fn);
|
GEN ("wire [31:0] i%i_l_adr, i%i_s_adr;\n", fn, fn);
|
|
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
|
GEN (" if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
|
GEN (" else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
|
GEN
|
|
(" else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
|
|
|
if (ci) {
|
if (ci)
|
|
{
|
GEN ("\n/* write register access */\n");
|
GEN ("\n/* write register access */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) begin\n");
|
GEN (" if (rst) begin\n");
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0; j < MAX_REGS; j++)
|
|
if (f[i]->used_regs[j])
|
GEN (" i%i_r%ii <= #Tp 32'h0;\n", fn, j);
|
GEN (" i%i_r%ii <= #Tp 32'h0;\n", fn, j);
|
GEN (" end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
|
GEN (" end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
|
GEN (" case (cuc_adr_i[5:0])\n");
|
GEN (" case (cuc_adr_i[5:0])\n");
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0; j < MAX_REGS; j++)
|
|
if (f[i]->used_regs[j])
|
GEN (" %-2i: i%i_r%ii <= #Tp cuc_dat_i;\n", j, fn, j);
|
GEN (" %-2i: i%i_r%ii <= #Tp cuc_dat_i;\n", j, fn, j);
|
GEN (" endcase\n");
|
GEN (" endcase\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
|
|
| Line 865... |
Line 1102... |
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) cuc_dat_o <= #Tp 32'h0;\n");
|
GEN (" if (rst) cuc_dat_o <= #Tp 32'h0;\n");
|
GEN (" else if (cuc_stb_i && cuc_we_i) begin\n");
|
GEN (" else if (cuc_stb_i && cuc_we_i) begin\n");
|
GEN (" ");
|
GEN (" ");
|
|
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++)
|
|
if (f[i])
|
|
{
|
co = 0;
|
co = 0;
|
for (j = 0; j < MAX_REGS; j++)
|
for (j = 0; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
|
co++;
|
|
|
GEN ("if (cuc_adr_i[15:6] == %i)", f[i]->tmp);
|
GEN ("if (cuc_adr_i[15:6] == %i)", f[i]->tmp);
|
if (co) {
|
if (co)
|
|
{
|
first = 1;
|
first = 1;
|
GEN ("\n case (cuc_adr_i[5:0])\n");
|
GEN ("\n case (cuc_adr_i[5:0])\n");
|
for (j = 0; j < MAX_REGS; j++)
|
for (j = 0; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
GEN (" %-2i: cuc_dat_o <= #Tp i%i_r%io;\n", j, f[i]->tmp, j);
|
GEN (" %-2i: cuc_dat_o <= #Tp i%i_r%io;\n", j,
|
|
f[i]->tmp, j);
|
GEN (" endcase\n");
|
GEN (" endcase\n");
|
} else {
|
}
|
|
else
|
|
{
|
GEN (" cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" cuc_dat_o <= #Tp 32'hx;\n");
|
}
|
}
|
GEN (" else ");
|
GEN (" else ");
|
}
|
}
|
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
|
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" end else cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" end else cuc_dat_o <= #Tp 32'hx;\n");
|
|
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("assign cuc_rdy_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
|
GEN
|
|
("assign cuc_rdy_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
|
}
|
}
|
|
|
/* Store/load Wishbone bridge */
|
/* Store/load Wishbone bridge */
|
for (j = 0; j < 2; j++) {
|
for (j = 0; j < 2; j++)
|
|
{
|
char t = j ? 's' : 'l';
|
char t = j ? 's' : 'l';
|
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
|
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
|
GEN ("reg [%i:0] %cm_sel;\n", log2_int (nrf), t);
|
GEN ("reg [%i:0] %cm_sel;\n", log2_int (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2_int (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2_int (nrf), t);
|
GEN ("reg %ccyc_ip;\n\n", t);
|
GEN ("reg %ccyc_ip;\n\n", t);
|
| Line 906... |
Line 1152... |
GEN (" %c_stb_o <= #Tp |i_%c_req;\n", t, t);
|
GEN (" %c_stb_o <= #Tp |i_%c_req;\n", t, t);
|
GEN ("end\n");
|
GEN ("end\n");
|
|
|
GEN ("\n/* highest bid */\n");
|
GEN ("\n/* highest bid */\n");
|
GEN ("always @(");
|
GEN ("always @(");
|
for (i = 0; i < nrf; i++) GEN ("%si_%c_req", i > 0 ? " or " : "", t);
|
for (i = 0; i < nrf; i++)
|
|
GEN ("%si_%c_req", i > 0 ? " or " : "", t);
|
GEN (")\n");
|
GEN (")\n");
|
for (i = 0; i < nrf; i++) GEN (" %sif (i_%c_req) %cm_bid = %i'h%x;\n",
|
for (i = 0; i < nrf; i++)
|
|
GEN (" %sif (i_%c_req) %cm_bid = %i'h%x;\n",
|
i ? "else " : "", t, t, log2_int (nrf) + 1, i);
|
i ? "else " : "", t, t, log2_int (nrf) + 1, i);
|
|
|
GEN ("\n/* selected transfer */\n");
|
GEN ("\n/* selected transfer */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2_int (nrf) + 1);
|
GEN (" if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2_int (nrf) + 1);
|
GEN (" else if (%c_rdy_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2_int (nrf) + 1);
|
GEN (" else if (%c_rdy_i) %cm_sel <= #Tp %i'h0;\n", t, t,
|
|
log2_int (nrf) + 1);
|
GEN (" else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
|
GEN (" else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
|
|
|
GEN ("\n/* Cycle */\n");
|
GEN ("\n/* Cycle */\n");
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
|
GEN (" if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
|
GEN (" else if (%c_rdy_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
|
GEN (" else if (%c_rdy_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
|
GEN (" else %ccyc_ip <= #Tp %c_cyc_o;\n", t, t);
|
GEN (" else %ccyc_ip <= #Tp %c_cyc_o;\n", t, t);
|
}
|
}
|
|
|
GEN ("\n/* Acknowledge */\n");
|
GEN ("\n/* Acknowledge */\n");
|
for (i = 0; i < nrf; i++) {
|
for (i = 0; i < nrf; i++)
|
GEN ("wire i%i_s_rdy = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & s_rdy_i;\n", i, i, i);
|
{
|
GEN ("wire i%i_l_rdy = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & l_rdy_i;\n", i, i, i);
|
GEN
|
|
("wire i%i_s_rdy = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & s_rdy_i;\n",
|
|
i, i, i);
|
|
GEN
|
|
("wire i%i_l_rdy = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & l_rdy_i;\n",
|
|
i, i, i);
|
}
|
}
|
|
|
GEN ("\n/* data, address selects and burst enables */\n");
|
GEN ("\n/* data, address selects and burst enables */\n");
|
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_s_dat;\n", i);
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++) GEN ("wire i%i_s_linbrst, i%i_l_linbrst;\n", i, i);
|
GEN ("wire [31:0] i%i_s_dat;\n", i);
|
for (i = 0; i < nrf; i++) GEN ("wire [3:0] i%i_s_sel, i%i_l_sel;\n", i, i);
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_l_dat = l_dat_i;\n", i);
|
GEN ("wire i%i_s_linbrst, i%i_l_linbrst;\n", i, i);
|
|
for (i = 0; i < nrf; i++)
|
|
GEN ("wire [3:0] i%i_s_sel, i%i_l_sel;\n", i, i);
|
|
for (i = 0; i < nrf; i++)
|
|
GEN ("wire [31:0] i%i_l_dat = l_dat_i;\n", i);
|
GEN ("\nalways @(posedge clk)\n");
|
GEN ("\nalways @(posedge clk)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" s_dat_o <= #Tp ");
|
GEN (" s_dat_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n sm_bid == %i ? i%i_s_dat : ", i, i);
|
GEN ("\n sm_bid == %i ? i%i_s_dat : ", i, i);
|
| Line 973... |
Line 1231... |
GEN ("i%i_l_linbrst;\n", nrf - 1);
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GEN ("i%i_l_linbrst;\n", nrf - 1);
|
GEN ("end\n\n");
|
GEN ("end\n\n");
|
|
|
/* start/end signals */
|
/* start/end signals */
|
GEN ("\n\n/* start/end signals */\n");
|
GEN ("\n\n/* start/end signals */\n");
|
for (i = 0; i < nrf; i++) {
|
for (i = 0; i < nrf; i++)
|
|
{
|
if (log2_int (maxncallees + 1))
|
if (log2_int (maxncallees + 1))
|
GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
|
GEN
|
|
("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
|
log2_int (maxncallees + 1), i, i, i, i);
|
log2_int (maxncallees + 1), i, i, i, i);
|
else GEN ("wire i%i_current = 0;\n", i);
|
else
|
|
GEN ("wire i%i_current = 0;\n", i);
|
}
|
}
|
GEN ("\n");
|
GEN ("\n");
|
|
|
for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0, j = 0; i < nfuncs; i++)
|
if (log2_int (ncallees[i])) {
|
if (f[i])
|
|
{
|
|
if (log2_int (ncallees[i]))
|
|
{
|
GEN ("reg [%i:0] i%i_start_bid;\n", log2_int (ncallees[i]), j);
|
GEN ("reg [%i:0] i%i_start_bid;\n", log2_int (ncallees[i]), j);
|
GEN ("always @(start%i", f[i]->tmp);
|
GEN ("always @(start%i", f[i]->tmp);
|
for (j = 0, first = 1; j < f[i]->nfdeps; j++)
|
for (j = 0, first = 1; j < f[i]->nfdeps; j++)
|
if (f[i]->fdeps[j]) GEN (", ");
|
if (f[i]->fdeps[j])
|
|
GEN (", ");
|
GEN (")\n");
|
GEN (")\n");
|
GEN ("begin !!!\n"); //TODO
|
GEN ("begin !!!\n"); //TODO
|
GEN (" \n");
|
GEN (" \n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
GEN ("wire i%i_start = main_start[%i];\n", j, j);
|
GEN ("wire i%i_start = main_start[%i];\n", j, j);
|
j++;
|
j++;
|
}
|
}
|
GEN ("\n");
|
GEN ("\n");
|
|
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++)
|
|
if (f[i])
|
|
{
|
int nf = f[i]->tmp;
|
int nf = f[i]->tmp;
|
GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename, prof_func[i].name, nf);
|
GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename,
|
GEN (" .l_adr_o(i%i_l_adr), .l_dat_i(i%i_l_dat), .l_req_o(i_l_req[%i]),\n",
|
prof_func[i].name, nf);
|
|
GEN
|
|
(" .l_adr_o(i%i_l_adr), .l_dat_i(i%i_l_dat), .l_req_o(i_l_req[%i]),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .l_sel_o(i%i_l_sel), .l_linbrst_o(i%i_l_linbrst), .l_rdy_i(i%i_l_rdy),\n",
|
GEN
|
|
(" .l_sel_o(i%i_l_sel), .l_linbrst_o(i%i_l_linbrst), .l_rdy_i(i%i_l_rdy),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .s_adr_o(i%i_s_adr), .s_dat_o(i%i_s_dat), .s_req_o(i_s_req[%i]),\n",
|
GEN
|
|
(" .s_adr_o(i%i_s_adr), .s_dat_o(i%i_s_dat), .s_req_o(i_s_req[%i]),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .s_sel_o(i%i_s_sel), .s_linbrst_o(i%i_s_linbrst), .s_rdy_i(i%i_s_rdy),\n",
|
GEN
|
|
(" .s_sel_o(i%i_s_sel), .s_linbrst_o(i%i_s_linbrst), .s_rdy_i(i%i_s_rdy),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" ");
|
GEN (" ");
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
|
if (f[i]->used_regs[j])
|
GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
|
GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
|
|
|
if (first) GEN ("\n ");
|
if (first)
|
|
GEN ("\n ");
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
GEN (".r%i_o(i%i_r%io), ", j, nf, j), first = 0;
|
GEN (".r%i_o(i%i_r%io), ", j, nf, j), first = 0;
|
if (first) GEN ("\n ");
|
if (first)
|
if (f[i]->nfdeps) {
|
GEN ("\n ");
|
GEN (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n", i, i, i),
|
if (f[i]->nfdeps)
|
GEN (" .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n");
|
{
|
GEN (" .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n ");
|
GEN
|
|
(".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n",
|
|
i, i, i),
|
|
GEN
|
|
(" .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n",
|
|
i, i, i, i); /* JPB guess at missing args */
|
|
GEN
|
|
(" .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n ",
|
|
i, i, i); /* JPB guess at missing args */
|
}
|
}
|
GEN (".start_i(i_start[%i]), .end_o(i_end[%i]), .busy_o(i_busy[%i]));\n", nf, nf, nf);
|
GEN
|
|
(".start_i(i_start[%i]), .end_o(i_end[%i]), .busy_o(i_busy[%i]));\n",
|
|
nf, nf, nf);
|
}
|
}
|
|
|
/* output footer */
|
/* output footer */
|
GEN ("\nendmodule\n");
|
GEN ("\nendmodule\n");
|
|
|
fclose (fo);
|
fclose (fo);
|
}
|
}
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
