| Line 62... |
Line 62... |
tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
|
tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
|
vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
|
vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
|
|
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < config.dmmu.nways; i++)
|
for (i = 0; i < config.dmmu.nways; i++)
|
if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
|
if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
|
(cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V))
|
(cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V))
|
way = i;
|
way = i;
|
|
|
/* Did we find our tlb entry? */
|
/* Did we find our tlb entry? */
|
if (way >= 0) { /* Yes, we did. */
|
if (way >= 0) { /* Yes, we did. */
|
| Line 84... |
Line 84... |
}
|
}
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (config.dmmu.nsets - 1) << 6;
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (config.dmmu.nsets - 1) << 6;
|
|
|
/* Check if page is cache inhibited */
|
/* Check if page is cache inhibited */
|
data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
|
data_ci = (cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
|
|
|
runtime.sim.mem_cycles += config.dmmu.hitdelay;
|
runtime.sim.mem_cycles += config.dmmu.hitdelay;
|
ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
|
ppn = cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] / config.dmmu.pagesize;
|
|
|
/* Test for page fault */
|
/* Test for page fault */
|
if (mfspr (SPR_SR) & SPR_SR_SM) {
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
|
if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
|
if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SWE)
|
|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
|
|| !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SRE))
|
except_handle(EXCEPT_DPF, virtaddr);
|
except_handle(EXCEPT_DPF, virtaddr);
|
} else {
|
} else {
|
if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
|
if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_UWE)
|
|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
|
|| !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_URE))
|
except_handle(EXCEPT_DPF, virtaddr);
|
except_handle(EXCEPT_DPF, virtaddr);
|
}
|
}
|
|
|
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
|
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
|
}
|
}
|
| Line 175... |
Line 175... |
tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
|
tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;
|
vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
|
vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);
|
|
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < config.dmmu.nways; i++)
|
for (i = 0; i < config.dmmu.nways; i++)
|
if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
|
if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&
|
(cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V))
|
(cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V))
|
way = i;
|
way = i;
|
|
|
/* Did we find our tlb entry? */
|
/* Did we find our tlb entry? */
|
if (way >= 0) { /* Yes, we did. */
|
if (way >= 0) { /* Yes, we did. */
|
dmmu_stats.loads_tlbhit++;
|
dmmu_stats.loads_tlbhit++;
|
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
runtime.sim.cycles);
|
runtime.sim.cycles);
|
|
|
/* Test for page fault */
|
/* Test for page fault */
|
if (mfspr (SPR_SR) & SPR_SR_SM) {
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
|
if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
|
if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SWE)
|
|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
|
|| !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SRE))
|
|
|
/* otherwise exception DPF would be raised */
|
/* otherwise exception DPF would be raised */
|
return(0);
|
return(0);
|
} else {
|
} else {
|
if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
|
if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_UWE)
|
|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
|
|| !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_URE))
|
|
|
/* otherwise exception DPF would be raised */
|
/* otherwise exception DPF would be raised */
|
return(0);
|
return(0);
|
}
|
}
|
|
|
if (through_dc) {
|
if (through_dc) {
|
/* Check if page is cache inhibited */
|
/* Check if page is cache inhibited */
|
data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
|
data_ci = (cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
|
}
|
}
|
|
|
ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
|
ppn = cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] / config.dmmu.pagesize;
|
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
|
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
|
}
|
}
|
else { /* No, we didn't. */
|
else { /* No, we didn't. */
|
return(0);
|
return(0);
|
}
|
}
|
