| Line 39... |
Line 39... |
#include "debug.h"
|
#include "debug.h"
|
#include "misc.h"
|
#include "misc.h"
|
|
|
DEFAULT_DEBUG_CHANNEL(dmmu);
|
DEFAULT_DEBUG_CHANNEL(dmmu);
|
|
|
/* Data MMU */
|
struct dmmu *dmmu_state;
|
|
|
|
/* Data MMU */
|
|
|
inline uorreg_t *dmmu_find_tlbmr(oraddr_t virtaddr, uorreg_t **dtlbmr_lru)
|
static inline uorreg_t *dmmu_find_tlbmr(oraddr_t virtaddr,
|
|
uorreg_t **dtlbmr_lru,
|
|
struct dmmu *dmmu)
|
{
|
{
|
int set;
|
int set;
|
int i;
|
int i;
|
oraddr_t vpn;
|
oraddr_t vpn;
|
uorreg_t *dtlbmr;
|
uorreg_t *dtlbmr;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = DADDR_PAGE(virtaddr) >> config.dmmu.pagesize_log2;
|
set = DADDR_PAGE(virtaddr) >> dmmu->pagesize_log2;
|
set &= config.dmmu.set_mask;
|
set &= dmmu->set_mask;
|
vpn = virtaddr & config.dmmu.vpn_mask;
|
vpn = virtaddr & dmmu->vpn_mask;
|
|
|
dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE(0) + set];
|
dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE(0) + set];
|
*dtlbmr_lru = dtlbmr;
|
*dtlbmr_lru = dtlbmr;
|
|
|
/* FIXME: Should this be reversed? */
|
/* FIXME: Should this be reversed? */
|
for(i = config.dmmu.nways; i; i--, dtlbmr += (128 * 2)) {
|
for(i = dmmu->nways; i; i--, dtlbmr += (128 * 2)) {
|
if(((*dtlbmr & config.dmmu.vpn_mask) == vpn) && (*dtlbmr & SPR_DTLBMR_V))
|
if(((*dtlbmr & dmmu->vpn_mask) == vpn) && (*dtlbmr & SPR_DTLBMR_V))
|
return dtlbmr;
|
return dtlbmr;
|
}
|
}
|
|
|
return NULL;
|
return NULL;
|
}
|
}
|
| Line 72... |
Line 75... |
{
|
{
|
int i;
|
int i;
|
uorreg_t *dtlbmr;
|
uorreg_t *dtlbmr;
|
uorreg_t *dtlbtr;
|
uorreg_t *dtlbtr;
|
uorreg_t *dtlbmr_lru;
|
uorreg_t *dtlbmr_lru;
|
|
struct dmmu *dmmu = dmmu_state;
|
|
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
|
!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
data_ci = (virtaddr >= 0x80000000);
|
data_ci = (virtaddr >= 0x80000000);
|
return virtaddr;
|
return virtaddr;
|
}
|
}
|
|
|
dtlbmr = dmmu_find_tlbmr(virtaddr, &dtlbmr_lru);
|
dtlbmr = dmmu_find_tlbmr(virtaddr, &dtlbmr_lru, dmmu);
|
|
|
/* Did we find our tlb entry? */
|
/* Did we find our tlb entry? */
|
if(dtlbmr) { /* Yes, we did. */
|
if(dtlbmr) { /* Yes, we did. */
|
dmmu_stats.loads_tlbhit++;
|
dmmu_stats.loads_tlbhit++;
|
|
|
| Line 91... |
Line 95... |
|
|
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
runtime.sim.cycles);
|
runtime.sim.cycles);
|
|
|
/* Set LRUs */
|
/* Set LRUs */
|
for(i = 0; i < config.dmmu.nways; i++, dtlbmr_lru += (128 * 2)) {
|
for(i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2)) {
|
if(*dtlbmr_lru & SPR_DTLBMR_LRU)
|
if(*dtlbmr_lru & SPR_DTLBMR_LRU)
|
*dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
|
*dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
|
((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);
|
((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);
|
}
|
}
|
|
|
/* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
|
/* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
|
* is always decremented and the number of sets is always a power of two and
|
* is always decremented and the number of sets is always a power of two and
|
* as such lru_reload has all bits set that get touched during decrementing
|
* as such lru_reload has all bits set that get touched during decrementing
|
* SPR_DTLBMR_LRU */
|
* SPR_DTLBMR_LRU */
|
*dtlbmr |= config.dmmu.lru_reload;
|
*dtlbmr |= dmmu->lru_reload;
|
|
|
/* Check if page is cache inhibited */
|
/* Check if page is cache inhibited */
|
data_ci = *dtlbtr & SPR_DTLBTR_CI;
|
data_ci = *dtlbtr & SPR_DTLBTR_CI;
|
|
|
runtime.sim.mem_cycles += config.dmmu.hitdelay;
|
runtime.sim.mem_cycles += dmmu->hitdelay;
|
|
|
/* Test for page fault */
|
/* Test for page fault */
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
|
if ( (write_access && !(*dtlbtr & SPR_DTLBTR_SWE))
|
if ( (write_access && !(*dtlbtr & SPR_DTLBTR_SWE))
|
|| (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
|
|| (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
|
| Line 120... |
Line 124... |
|| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
|
|| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
|
except_handle(EXCEPT_DPF, virtaddr);
|
except_handle(EXCEPT_DPF, virtaddr);
|
}
|
}
|
|
|
TRACE("Returning physical address %"PRIxADDR"\n",
|
TRACE("Returning physical address %"PRIxADDR"\n",
|
(*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
|
(*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr & (dmmu->page_offset_mask)));
|
(config.dmmu.page_offset_mask)));
|
return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr & (dmmu->page_offset_mask));
|
return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
|
|
(config.dmmu.page_offset_mask));
|
|
}
|
}
|
|
|
/* No, we didn't. */
|
/* No, we didn't. */
|
dmmu_stats.loads_tlbmiss++;
|
dmmu_stats.loads_tlbmiss++;
|
#if 0
|
#if 0
|
for (i = 0; i < config.dmmu.nways; i++)
|
for (i = 0; i < dmmu->nways; i++)
|
if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_LRU) >> 6) < minlru)
|
if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_LRU) >> 6) < minlru)
|
minway = i;
|
minway = i;
|
|
|
cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] &= ~SPR_DTLBMR_VPN;
|
cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] &= ~SPR_DTLBMR_VPN;
|
cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= vpn << 12;
|
cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= vpn << 12;
|
for (i = 0; i < config.dmmu.nways; i++) {
|
for (i = 0; i < dmmu->nways; i++) {
|
uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE(i) + set];
|
uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE(i) + set];
|
if (lru & SPR_DTLBMR_LRU) {
|
if (lru & SPR_DTLBMR_LRU) {
|
lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40);
|
lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40);
|
cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] = lru;
|
cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] = lru;
|
}
|
}
|
}
|
}
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (config.dmmu.nsets - 1) << 6;
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (dmmu->nsets - 1) << 6;
|
|
|
/* 1 to 1 mapping */
|
/* 1 to 1 mapping */
|
cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] &= ~SPR_DTLBTR_PPN;
|
cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] &= ~SPR_DTLBTR_PPN;
|
cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] |= vpn << 12;
|
cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] |= vpn << 12;
|
|
|
cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= SPR_DTLBMR_V;
|
cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= SPR_DTLBMR_V;
|
#endif
|
#endif
|
TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
|
runtime.sim.cycles);
|
runtime.sim.cycles);
|
runtime.sim.mem_cycles += config.dmmu.missdelay;
|
runtime.sim.mem_cycles += dmmu->missdelay;
|
/* if tlb refill implemented in HW */
|
/* if tlb refill implemented in HW */
|
/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
|
/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */
|
|
|
except_handle(EXCEPT_DTLBMISS, virtaddr);
|
except_handle(EXCEPT_DTLBMISS, virtaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
| Line 183... |
Line 185... |
oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)
|
oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)
|
{
|
{
|
uorreg_t *dtlbmr;
|
uorreg_t *dtlbmr;
|
uorreg_t *dtlbtr;
|
uorreg_t *dtlbtr;
|
uorreg_t *dtlbmr_lru;
|
uorreg_t *dtlbmr_lru;
|
|
struct dmmu *dmmu = dmmu_state;
|
|
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
|
!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
if (through_dc)
|
if (through_dc)
|
data_ci = (virtaddr >= 0x80000000);
|
data_ci = (virtaddr >= 0x80000000);
|
return virtaddr;
|
return virtaddr;
|
}
|
}
|
|
|
dtlbmr = dmmu_find_tlbmr(virtaddr, &dtlbmr_lru);
|
dtlbmr = dmmu_find_tlbmr(virtaddr, &dtlbmr_lru, dmmu);
|
|
|
/* Did we find our tlb entry? */
|
/* Did we find our tlb entry? */
|
if (dtlbmr) { /* Yes, we did. */
|
if (dtlbmr) { /* Yes, we did. */
|
dmmu_stats.loads_tlbhit++;
|
dmmu_stats.loads_tlbhit++;
|
|
|
| Line 222... |
Line 225... |
if (through_dc) {
|
if (through_dc) {
|
/* Check if page is cache inhibited */
|
/* Check if page is cache inhibited */
|
data_ci = *dtlbtr & SPR_DTLBTR_CI;
|
data_ci = *dtlbtr & SPR_DTLBTR_CI;
|
}
|
}
|
|
|
return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
|
return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr & (dmmu->page_offset_mask));
|
(config.dmmu.page_offset_mask));
|
|
}
|
}
|
|
|
return(0);
|
return(0);
|
}
|
}
|
|
|
|
/* FIXME: Is this comment valid? */
|
void dtlb_info(void)
|
|
{
|
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
|
PRINTF("DMMU not implemented. Set UPR[DMP].\n");
|
|
return;
|
|
}
|
|
|
|
PRINTF("Data MMU %dKB: ", config.dmmu.nsets * config.dmmu.entrysize * config.dmmu.nways / 1024);
|
|
PRINTF("%d ways, %d sets, entry size %d bytes\n", config.dmmu.nways, config.dmmu.nsets, config.dmmu.entrysize);
|
|
}
|
|
|
|
/* First check if virtual address is covered by DTLB and if it is:
|
/* First check if virtual address is covered by DTLB and if it is:
|
- increment DTLB read hit stats,
|
- increment DTLB read hit stats,
|
- set 'lru' at this way to config.dmmu.ustates - 1 and
|
- set 'lru' at this way to dmmu->ustates - 1 and
|
decrement 'lru' of other ways unless they have reached 0,
|
decrement 'lru' of other ways unless they have reached 0,
|
- check page access attributes and invoke DMMU page fault exception
|
- check page access attributes and invoke DMMU page fault exception
|
handler if necessary
|
handler if necessary
|
and if not:
|
and if not:
|
- increment DTLB read miss stats
|
- increment DTLB read miss stats
|
- find lru way and entry and invoke DTLB miss exception handler
|
- find lru way and entry and invoke DTLB miss exception handler
|
- set 'lru' with config.dmmu.ustates - 1 and decrement 'lru' of other
|
- set 'lru' with dmmu->ustates - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
|
*/
|
*/
|
|
|
void dtlb_status(int start_set)
|
static void dtlb_status(void *dat)
|
{
|
{
|
|
struct dmmu *dmmu = dat;
|
int set;
|
int set;
|
int way;
|
int way;
|
int end_set = config.dmmu.nsets;
|
int end_set = dmmu->nsets;
|
|
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
PRINTF("DMMU not implemented. Set UPR[DMP].\n");
|
PRINTF("DMMU not implemented. Set UPR[DMP].\n");
|
return;
|
return;
|
}
|
}
|
|
|
if ((start_set >= 0) && (start_set < end_set))
|
if (0 < end_set) PRINTF("\nDMMU: ");
|
end_set = start_set + 1;
|
|
else
|
|
start_set = 0;
|
|
|
|
if (start_set < end_set) PRINTF("\nDMMU: ");
|
|
/* Scan set(s) and way(s). */
|
/* Scan set(s) and way(s). */
|
for (set = start_set; set < end_set; set++) {
|
for (set = 0; set < end_set; set++) {
|
PRINTF("\nSet %x: ", set);
|
for (way = 0; way < dmmu->nways; way++) {
|
for (way = 0; way < config.dmmu.nways; way++) {
|
|
PRINTF(" way %d: ", way);
|
|
PRINTF("%s\n", dump_spr(SPR_DTLBMR_BASE(way) + set,
|
PRINTF("%s\n", dump_spr(SPR_DTLBMR_BASE(way) + set,
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set]));
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set]));
|
PRINTF("%s\n", dump_spr(SPR_DTLBTR_BASE(way) + set,
|
PRINTF("%s\n", dump_spr(SPR_DTLBTR_BASE(way) + set,
|
cpu_state.sprs[SPR_DTLBTR_BASE(way) + set]));
|
cpu_state.sprs[SPR_DTLBTR_BASE(way) + set]));
|
}
|
}
|
}
|
}
|
if (start_set < end_set) PRINTF("\n");
|
if (0 < end_set) PRINTF("\n");
|
}
|
}
|
|
|
/*---------------------------------------------------[ DMMU configuration ]---*/
|
/*---------------------------------------------------[ DMMU configuration ]---*/
|
static void dmmu_enabled(union param_val val, void *dat)
|
static void dmmu_enabled(union param_val val, void *dat)
|
{
|
{
|
|
struct dmmu *dmmu = dat;
|
|
|
if(val.int_val)
|
if(val.int_val)
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
|
else
|
else
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
|
config.dmmu.enabled = val.int_val;
|
dmmu->enabled = val.int_val;
|
}
|
}
|
|
|
static void dmmu_nsets(union param_val val, void *dat)
|
static void dmmu_nsets(union param_val val, void *dat)
|
{
|
{
|
|
struct dmmu *dmmu = dat;
|
|
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
config.dmmu.nsets = val.int_val;
|
dmmu->nsets = val.int_val;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
|
cpu_state.sprs[SPR_DMMUCFGR] |= log2_int(val.int_val) << 3;
|
cpu_state.sprs[SPR_DMMUCFGR] |= log2_int(val.int_val) << 3;
|
} else
|
} else
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
}
|
}
|
|
|
static void dmmu_nways(union param_val val, void *dat)
|
static void dmmu_nways(union param_val val, void *dat)
|
{
|
{
|
|
struct dmmu *dmmu = dat;
|
|
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
config.dmmu.nways = val.int_val;
|
dmmu->nways = val.int_val;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
|
cpu_state.sprs[SPR_DMMUCFGR] |= val.int_val - 1;
|
cpu_state.sprs[SPR_DMMUCFGR] |= val.int_val - 1;
|
}
|
}
|
else
|
else
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
}
|
}
|
|
|
static void dmmu_pagesize(union param_val val, void *dat)
|
static void dmmu_pagesize(union param_val val, void *dat)
|
{
|
{
|
|
struct dmmu *dmmu = dat;
|
|
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.dmmu.pagesize = val.int_val;
|
dmmu->pagesize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
static void dmmu_entrysize(union param_val val, void *dat)
|
static void dmmu_entrysize(union param_val val, void *dat)
|
{
|
{
|
|
struct dmmu *dmmu = dat;
|
|
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.dmmu.entrysize = val.int_val;
|
dmmu->entrysize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
static void dmmu_ustates(union param_val val, void *dat)
|
static void dmmu_ustates(union param_val val, void *dat)
|
{
|
{
|
|
struct dmmu *dmmu = dat;
|
|
|
if (val.int_val >= 2 && val.int_val <= 4)
|
if (val.int_val >= 2 && val.int_val <= 4)
|
config.dmmu.ustates = val.int_val;
|
dmmu->ustates = val.int_val;
|
else
|
else
|
CONFIG_ERROR("invalid USTATE.");
|
CONFIG_ERROR("invalid USTATE.");
|
}
|
}
|
|
|
static void dmmu_missdelay(union param_val val, void *dat)
|
static void dmmu_missdelay(union param_val val, void *dat)
|
{
|
{
|
config.dmmu.missdelay = val.int_val;
|
struct dmmu *dmmu = dat;
|
|
|
|
dmmu->missdelay = val.int_val;
|
}
|
}
|
|
|
static void dmmu_hitdelay(union param_val val, void *dat)
|
static void dmmu_hitdelay(union param_val val, void *dat)
|
{
|
{
|
config.dmmu.hitdelay = val.int_val;
|
struct dmmu *dmmu = dat;
|
|
|
|
dmmu->hitdelay = val.int_val;
|
}
|
}
|
|
|
static void *dmmu_start_sec(void)
|
static void *dmmu_start_sec(void)
|
{
|
{
|
return NULL;
|
struct dmmu *dmmu;
|
|
|
|
if(!(dmmu = malloc(sizeof(struct dmmu)))) {
|
|
fprintf(stderr, "OOM\n");
|
|
exit(1);
|
|
}
|
|
|
|
dmmu->enabled = 0;
|
|
dmmu->hitdelay = 1;
|
|
dmmu->missdelay = 1;
|
|
dmmu->pagesize = 8192;
|
|
/* FIXME: Something sane */
|
|
dmmu->entrysize = 0;
|
|
|
|
dmmu_state = dmmu;
|
|
|
|
return dmmu;
|
}
|
}
|
|
|
static void dmmu_end_sec(void *dat)
|
static void dmmu_end_sec(void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
/* Precalculate some values for use during address translation */
|
/* Precalculate some values for use during address translation */
|
config.dmmu.pagesize_log2 = log2_int(config.dmmu.pagesize);
|
dmmu->pagesize_log2 = log2_int(dmmu->pagesize);
|
config.dmmu.page_offset_mask = config.dmmu.pagesize - 1;
|
dmmu->page_offset_mask = dmmu->pagesize - 1;
|
config.dmmu.page_mask = ~config.dmmu.page_offset_mask;
|
dmmu->page_mask = ~dmmu->page_offset_mask;
|
config.dmmu.vpn_mask = ~((config.dmmu.pagesize * config.dmmu.nsets) - 1);
|
dmmu->vpn_mask = ~((dmmu->pagesize * dmmu->nsets) - 1);
|
config.dmmu.set_mask = config.dmmu.nsets - 1;
|
dmmu->set_mask = dmmu->nsets - 1;
|
config.dmmu.lru_reload = (config.dmmu.set_mask << 6) & SPR_DTLBMR_LRU;
|
dmmu->lru_reload = (dmmu->set_mask << 6) & SPR_DTLBMR_LRU;
|
|
|
|
if(dmmu->enabled) {
|
|
PRINTF("Data MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
|
|
dmmu->nsets * dmmu->entrysize * dmmu->nways / 1024, dmmu->nways,
|
|
dmmu->nsets, dmmu->entrysize);
|
|
reg_sim_stat(dtlb_status, dmmu);
|
|
}
|
}
|
}
|
|
|
void reg_dmmu_sec(void)
|
void reg_dmmu_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("dmmu", dmmu_start_sec,
|
struct config_section *sec = reg_config_sec("dmmu", dmmu_start_sec,
|
