| Line 35... |
Line 35... |
|
|
/* Package includes */
|
/* Package includes */
|
#include "dmmu.h"
|
#include "dmmu.h"
|
#include "sim-config.h"
|
#include "sim-config.h"
|
#include "arch.h"
|
#include "arch.h"
|
#include "debug.h"
|
|
#include "execute.h"
|
#include "execute.h"
|
#include "spr-defs.h"
|
#include "spr-defs.h"
|
#include "stats.h"
|
#include "stats.h"
|
#include "except.h"
|
#include "except.h"
|
#include "sprs.h"
|
#include "sprs.h"
|
#include "misc.h"
|
#include "misc.h"
|
#include "sim-cmd.h"
|
#include "sim-cmd.h"
|
|
|
|
|
DEFAULT_DEBUG_CHANNEL (dmmu);
|
|
|
|
struct dmmu *dmmu_state;
|
struct dmmu *dmmu_state;
|
|
|
/* Data MMU */
|
/* Data MMU */
|
|
|
static uorreg_t *
|
static uorreg_t *
|
| Line 102... |
Line 99... |
{ /* Yes, we did. */
|
{ /* Yes, we did. */
|
dmmu_stats.loads_tlbhit++;
|
dmmu_stats.loads_tlbhit++;
|
|
|
dtlbtr = dtlbmr + 128;
|
dtlbtr = dtlbmr + 128;
|
|
|
TRACE ("DTLB hit (virtaddr=%" PRIxADDR ") at %lli.\n", virtaddr,
|
|
runtime.sim.cycles);
|
|
|
|
/* Set LRUs */
|
/* Set LRUs */
|
for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))
|
for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))
|
{
|
{
|
if (*dtlbmr_lru & SPR_DTLBMR_LRU)
|
if (*dtlbmr_lru & SPR_DTLBMR_LRU)
|
*dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
|
*dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
|
| Line 138... |
Line 132... |
if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE))
|
if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE))
|
|| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
|
|| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
|
except_handle (EXCEPT_DPF, virtaddr);
|
except_handle (EXCEPT_DPF, virtaddr);
|
}
|
}
|
|
|
TRACE ("Returning physical address %" PRIxADDR "\n",
|
|
(*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
|
|
(dmmu->page_offset_mask)));
|
|
return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
|
return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
|
(dmmu->page_offset_mask));
|
(dmmu->page_offset_mask));
|
}
|
}
|
|
|
/* No, we didn't. */
|
/* No, we didn't. */
|
| Line 173... |
Line 164... |
cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] &= ~SPR_DTLBTR_PPN;
|
cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] &= ~SPR_DTLBTR_PPN;
|
cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] |= vpn << 12;
|
cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] |= vpn << 12;
|
|
|
cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= SPR_DTLBMR_V;
|
cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= SPR_DTLBMR_V;
|
#endif
|
#endif
|
TRACE ("DTLB miss (virtaddr=%" PRIxADDR ") at %lli.\n", virtaddr,
|
|
runtime.sim.cycles);
|
|
runtime.sim.mem_cycles += dmmu->missdelay;
|
runtime.sim.mem_cycles += dmmu->missdelay;
|
/* if tlb refill implemented in HW */
|
/* if tlb refill implemented in HW */
|
/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */
|
/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */
|
|
|
except_handle (EXCEPT_DTLBMISS, virtaddr);
|
except_handle (EXCEPT_DTLBMISS, virtaddr);
|
| Line 225... |
Line 214... |
{ /* Yes, we did. */
|
{ /* Yes, we did. */
|
dmmu_stats.loads_tlbhit++;
|
dmmu_stats.loads_tlbhit++;
|
|
|
dtlbtr = dtlbmr + 128;
|
dtlbtr = dtlbmr + 128;
|
|
|
TRACE ("DTLB hit (virtaddr=%" PRIxADDR ") at %lli.\n", virtaddr,
|
|
runtime.sim.cycles);
|
|
|
|
/* Test for page fault */
|
/* Test for page fault */
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
|
{
|
{
|
if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) ||
|
if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) ||
|
(!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
|
(!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
|
