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[/] [or1k/] [trunk/] [or1ksim/] [mmu/] [dmmu.c] - Diff between revs 430 and 438
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Rev 430 |
Rev 438 |
Line 56... |
Line 56... |
dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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debug(5, "DTLB hit (virtaddr=%x).\n", virtaddr);
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debug(5, "DTLB hit (virtaddr=%x).\n", virtaddr);
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/* Test for page fault */
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/* Test for page fault */
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if (mfspr (SPR_SR) & SPR_SR_SUPV) {
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if (mfspr (SPR_SR) & SPR_SR_SUPV) {
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if ( write_access && !(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SWE)
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)
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|| !write_access && !(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SRE))
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))
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except_handle(EXCEPT_DPF, virtaddr);
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except_handle(EXCEPT_DPF, virtaddr);
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} else {
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} else {
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if ( write_access && !(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UWE)
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if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)
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|| !write_access && !(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_URE))
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|| !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))
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except_handle(EXCEPT_DPF, virtaddr);
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except_handle(EXCEPT_DPF, virtaddr);
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}
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}
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/* Set LRUs */
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/* Set LRUs */
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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