| Line 32... |
Line 32... |
/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */
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/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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/* all user defineable settings are in 'atahost_define.h' */
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#include "atahost_define.h"
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#include "atahost.h"
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#include "atahost.h"
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/* default timing reset values */
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#define PIO_MODE0_T1 6
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#define PIO_MODE0_T2 28
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#define PIO_MODE0_T4 2
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#define PIO_MODE0_TEOC 23
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#define DMA_MODE0_TM 4
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#define DMA_MODE0_TD 21
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#define DMA_MODE0_TEOC 21
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/* reset and initialize ATA host core(s) */
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/* reset and initialize ATA host core(s) */
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static void ata_reset(void *dat)
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static void ata_reset(void *dat)
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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// reset the core registers
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// reset the core registers
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ata->regs.ctrl = 0x0001;
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ata->regs.ctrl = 0x0001;
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ata->regs.stat = (ata->dev_id << 28) | (ata->rev << 24);
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ata->regs.stat = (ata->dev_id << 28) | (ata->rev << 24);
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ata->regs.pctr = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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ata->regs.pctr = (ata->pio_mode0_teoc << ATA_TEOC) |
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ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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(ata->pio_mode0_t4 << ATA_T4) |
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ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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(ata->pio_mode0_t2 << ATA_T2) |
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ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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(ata->pio_mode0_t1 << ATA_T1);
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ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.pftr0 = ata->regs.pctr;
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ata->regs.pftr1 = ata->regs.pctr;
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ata->regs.dtr0 = (ata->dma_mode0_teoc << ATA_TEOC) |
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(ata->dma_mode0_td << ATA_TD) |
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(ata->dma_mode0_tm << ATA_TM);
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ata->regs.dtr1 = ata->regs.dtr0;
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ata->regs.txb = 0;
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ata->regs.txb = 0;
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// inform simulator about new read/write delay timings
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// inform simulator about new read/write delay timings
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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| Line 267... |
Line 280... |
{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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ata->rev = val.int_val;
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ata->rev = val.int_val;
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}
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}
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static void ata_pio_mode0_t1(union param_val val, void *dat)
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{
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ata_host *ata = dat;
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if(val.int_val < 0 || val.int_val > 255) {
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fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t1: %d\n", val.int_val);
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return;
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}
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ata->pio_mode0_t1 = val.int_val;
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}
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static void ata_pio_mode0_t2(union param_val val, void *dat)
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{
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ata_host *ata = dat;
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if(val.int_val < 0 || val.int_val > 255) {
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fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t2: %d\n", val.int_val);
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return;
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}
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ata->pio_mode0_t2 = val.int_val;
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}
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static void ata_pio_mode0_t4(union param_val val, void *dat)
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{
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ata_host *ata = dat;
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if(val.int_val < 0 || val.int_val > 255) {
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fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_t4: %d\n", val.int_val);
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return;
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}
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ata->pio_mode0_t4 = val.int_val;
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}
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static void ata_pio_mode0_teoc(union param_val val, void *dat)
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{
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ata_host *ata = dat;
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if(val.int_val < 0 || val.int_val > 255) {
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fprintf(stderr, "Peripheral ATA: Invalid pio_mode0_teoc: %d\n", val.int_val);
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return;
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}
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ata->pio_mode0_teoc = val.int_val;
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}
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static void ata_dma_mode0_tm(union param_val val, void *dat)
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{
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ata_host *ata = dat;
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if(val.int_val < 0 || val.int_val > 255) {
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fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_tm: %d\n", val.int_val);
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return;
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}
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ata->dma_mode0_tm = val.int_val;
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}
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static void ata_dma_mode0_td(union param_val val, void *dat)
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{
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ata_host *ata = dat;
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if(val.int_val < 0 || val.int_val > 255) {
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fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_td: %d\n", val.int_val);
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return;
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}
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ata->dma_mode0_td = val.int_val;
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}
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static void ata_dma_mode0_teoc(union param_val val, void *dat)
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{
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ata_host *ata = dat;
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if(val.int_val < 0 || val.int_val > 255) {
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fprintf(stderr, "Peripheral ATA: Invalid dma_mode0_teoc: %d\n", val.int_val);
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return;
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}
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ata->dma_mode0_teoc = val.int_val;
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}
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static void ata_dev_type0(union param_val val, void *dat)
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static void ata_dev_type0(union param_val val, void *dat)
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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ata->devices.device[0].conf.type = val.int_val;
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ata->devices.device[0].conf.type = val.int_val;
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}
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}
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| Line 340... |
Line 437... |
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memset(new, 0, sizeof(ata_host));
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memset(new, 0, sizeof(ata_host));
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new->enabled = 1;
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new->enabled = 1;
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new->dev_id = 1;
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new->dev_id = 1;
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new->pio_mode0_t1 = PIO_MODE0_T1;
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new->pio_mode0_t2 = PIO_MODE0_T2;
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new->pio_mode0_t4 = PIO_MODE0_T4;
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new->pio_mode0_teoc = PIO_MODE0_TEOC;
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new->dma_mode0_tm = DMA_MODE0_TM;
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new->dma_mode0_td = DMA_MODE0_TD;
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new->dma_mode0_teoc = DMA_MODE0_TEOC;
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return new;
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return new;
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}
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}
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static void ata_sec_end(void *dat)
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static void ata_sec_end(void *dat)
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{
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{
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| Line 383... |
Line 489... |
reg_config_param(sec, "baseaddr", paramt_addr, ata_baseaddr);
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reg_config_param(sec, "baseaddr", paramt_addr, ata_baseaddr);
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reg_config_param(sec, "irq", paramt_int, ata_irq);
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reg_config_param(sec, "irq", paramt_int, ata_irq);
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reg_config_param(sec, "dev_id", paramt_int, ata_dev_id);
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reg_config_param(sec, "dev_id", paramt_int, ata_dev_id);
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reg_config_param(sec, "rev", paramt_int, ata_rev);
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reg_config_param(sec, "rev", paramt_int, ata_rev);
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reg_config_param(sec, "pio_mode0_t1", paramt_int, ata_pio_mode0_t1);
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reg_config_param(sec, "pio_mode0_t2", paramt_int, ata_pio_mode0_t2);
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reg_config_param(sec, "pio_mode0_t4", paramt_int, ata_pio_mode0_t4);
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reg_config_param(sec, "pio_mode0_teoc", paramt_int, ata_pio_mode0_teoc);
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reg_config_param(sec, "dma_mode0_tm", paramt_int, ata_dma_mode0_tm);
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reg_config_param(sec, "dma_mode0_td", paramt_int, ata_dma_mode0_td);
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reg_config_param(sec, "dma_mode0_teoc", paramt_int, ata_dma_mode0_teoc);
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reg_config_param(sec, "dev_type0", paramt_int, ata_dev_type0);
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reg_config_param(sec, "dev_type0", paramt_int, ata_dev_type0);
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reg_config_param(sec, "dev_file0", paramt_str, ata_dev_file0);
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reg_config_param(sec, "dev_file0", paramt_str, ata_dev_file0);
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reg_config_param(sec, "dev_size0", paramt_int, ata_dev_size0);
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reg_config_param(sec, "dev_size0", paramt_int, ata_dev_size0);
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reg_config_param(sec, "dev_packet0", paramt_int, ata_dev_packet0);
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reg_config_param(sec, "dev_packet0", paramt_int, ata_dev_packet0);
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reg_config_param(sec, "dev_type1", paramt_int, ata_dev_type1);
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reg_config_param(sec, "dev_type1", paramt_int, ata_dev_type1);
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