| Line 32... |
Line 32... |
#include <stdlib.h>
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#include <stdlib.h>
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/* Package includes */
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/* Package includes */
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#include "atahost.h"
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#include "atahost.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "pic.h"
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#include "pic.h"
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#include "toplevel-support.h"
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#include "toplevel-support.h"
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#include "sim-cmd.h"
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#include "sim-cmd.h"
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| Line 49... |
Line 48... |
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#define DMA_MODE0_TM 4
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#define DMA_MODE0_TM 4
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#define DMA_MODE0_TD 21
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#define DMA_MODE0_TD 21
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#define DMA_MODE0_TEOC 21
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#define DMA_MODE0_TEOC 21
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DEFAULT_DEBUG_CHANNEL (ata);
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/* reset and initialize ATA host core(s) */
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/* reset and initialize ATA host core(s) */
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static void
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static void
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ata_reset (void *dat)
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ata_reset (void *dat)
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{
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{
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| Line 113... |
Line 111... |
adjust_rw_delay (ata->mem, 2, 2);
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adjust_rw_delay (ata->mem, 2, 2);
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switch (addr)
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switch (addr)
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{
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{
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case ATA_CTRL:
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case ATA_CTRL:
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TRACE ("Read control register: %" PRIx32 "\n", ata->regs.ctrl);
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return ata->regs.ctrl;
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return ata->regs.ctrl;
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case ATA_STAT:
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case ATA_STAT:
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return ata->regs.stat;
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return ata->regs.stat;
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| Line 184... |
Line 181... |
adjust_rw_delay (ata->mem, 2, 2);
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adjust_rw_delay (ata->mem, 2, 2);
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switch (addr)
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switch (addr)
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{
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{
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case ATA_CTRL:
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case ATA_CTRL:
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TRACE ("Writting control register: %" PRIx32 "\n", value);
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ata->regs.ctrl = value;
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ata->regs.ctrl = value;
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/* check if reset bit set, if so reset ata-devices */
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/* check if reset bit set, if so reset ata-devices */
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if (value & ATA_RST)
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if (value & ATA_RST)
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ata_devices_hw_reset (&ata->devices, 1);
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ata_devices_hw_reset (&ata->devices, 1);
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| Line 203... |
Line 199... |
ata->regs.stat &= ~ATA_IDEIS;
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ata->regs.stat &= ~ATA_IDEIS;
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}
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}
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break;
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break;
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case ATA_PCTR:
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case ATA_PCTR:
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TRACE ("PCTR: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
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value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
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value & 0xff);
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ata->regs.pctr = value;
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ata->regs.pctr = value;
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break;
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break;
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case ATA_PFTR0:
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case ATA_PFTR0:
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TRACE ("PFTR0: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
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value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
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value & 0xff);
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ata->regs.pftr0 = value;
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ata->regs.pftr0 = value;
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break;
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break;
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case ATA_PFTR1:
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case ATA_PFTR1:
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TRACE ("PFTR1: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
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value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
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value & 0xff);
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ata->regs.pftr1 = value;
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ata->regs.pftr1 = value;
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break;
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break;
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case ATA_DTR0:
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case ATA_DTR0:
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ata->regs.dtr0 = value;
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ata->regs.dtr0 = value;
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| Line 286... |
Line 273... |
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if (ata->baseaddr == 0)
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if (ata->baseaddr == 0)
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return;
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return;
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PRINTF ("\nOCIDEC-%1d at: 0x%" PRIxADDR "\n", ata->dev_id, ata->baseaddr);
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PRINTF ("\nOCIDEC-%1d at: 0x%" PRIxADDR "\n", ata->dev_id, ata->baseaddr);
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PRINTF ("ATA CTRL : 0x%08X\n", ata->regs.ctrl);
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PRINTF ("ATA CTRL : 0x%08" PRIx32 "\n", ata->regs.ctrl);
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PRINTF ("ATA STAT : 0x%08x\n", ata->regs.stat);
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PRINTF ("ATA STAT : 0x%08" PRIx32 "\n", ata->regs.stat);
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PRINTF ("ATA PCTR : 0x%08x\n", ata->regs.pctr);
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PRINTF ("ATA PCTR : 0x%08" PRIx32 "n", ata->regs.pctr);
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if (ata->dev_id > 1)
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if (ata->dev_id > 1)
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{
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{
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PRINTF ("ATA FCTR0 : 0x%08x\n", ata->regs.pftr0);
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PRINTF ("ATA FCTR0 : 0x%08" PRIx32 "\n", ata->regs.pftr0);
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PRINTF ("ATA FCTR1 : 0x%08x\n", ata->regs.pftr1);
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PRINTF ("ATA FCTR1 : 0x%08" PRIx32 "\n", ata->regs.pftr1);
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}
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}
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if (ata->dev_id > 2)
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if (ata->dev_id > 2)
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{
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{
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PRINTF ("ATA DTR0 : 0x%08x\n", ata->regs.dtr0);
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PRINTF ("ATA DTR0 : 0x%08" PRIx32 "\n", ata->regs.dtr0);
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PRINTF ("ATA DTR1 : 0x%08x\n", ata->regs.dtr1);
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PRINTF ("ATA DTR1 : 0x%08" PRIx32 "\n", ata->regs.dtr1);
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PRINTF ("ATA TXD : 0x%08x\n", ata->regs.txb);
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PRINTF ("ATA TXD : 0x%08" PRIx32 "\n", ata->regs.txb);
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PRINTF ("ATA RXD : 0x%08x\n", ata->regs.rxb);
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PRINTF ("ATA RXD : 0x%08" PRIx32 "\n", ata->regs.rxb);
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}
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}
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}
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}
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/* ========================================================================= */
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/* ========================================================================= */
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