Line 80... |
Line 80... |
/* Wishbone read */
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/* Wishbone read */
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uint32_t gpio_read32( oraddr_t addr, void *dat )
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uint32_t gpio_read32( oraddr_t addr, void *dat )
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{
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{
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struct gpio_device *gpio = dat;
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struct gpio_device *gpio = dat;
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addr -= gpio->baseaddr;
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switch( addr ) {
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switch( addr ) {
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case RGPIO_IN: return gpio->curr.in | gpio->curr.out;
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case RGPIO_IN: return gpio->curr.in | gpio->curr.out;
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case RGPIO_OUT: return gpio->curr.out;
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case RGPIO_OUT: return gpio->curr.out;
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case RGPIO_OE: return gpio->curr.oe;
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case RGPIO_OE: return gpio->curr.oe;
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case RGPIO_INTE: return gpio->curr.inte;
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case RGPIO_INTE: return gpio->curr.inte;
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Line 102... |
Line 100... |
/* Wishbone write */
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/* Wishbone write */
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void gpio_write32( oraddr_t addr, uint32_t value, void *dat )
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void gpio_write32( oraddr_t addr, uint32_t value, void *dat )
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{
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{
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struct gpio_device *gpio = dat;
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struct gpio_device *gpio = dat;
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addr -= gpio->baseaddr;
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switch( addr ) {
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switch( addr ) {
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case RGPIO_IN: debug( 5, "GPIO: Cannot write to RGPIO_IN\n" ); break;
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case RGPIO_IN: debug( 5, "GPIO: Cannot write to RGPIO_IN\n" ); break;
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case RGPIO_OUT: gpio->next.out = value; break;
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case RGPIO_OUT: gpio->next.out = value; break;
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case RGPIO_OE: gpio->next.oe = value; break;
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case RGPIO_OE: gpio->next.oe = value; break;
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case RGPIO_INTE: gpio->next.inte = value; break;
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case RGPIO_INTE: gpio->next.inte = value; break;
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Line 275... |
Line 271... |
}
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}
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void gpio_sec_end(void *dat)
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void gpio_sec_end(void *dat)
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{
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{
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struct gpio_device *gpio = dat;
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struct gpio_device *gpio = dat;
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struct mem_ops ops;
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if(!gpio->enabled) {
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if(!gpio->enabled) {
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free(dat);
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free(dat);
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return;
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return;
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}
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}
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memset(&ops, 0, sizeof(struct mem_ops));
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ops.readfunc32 = gpio_read32;
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ops.writefunc32 = gpio_write32;
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ops.write_dat32 = dat;
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ops.read_dat32 = dat;
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/* FIXME: Correct delays? */
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ops.delayr = 2;
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ops.delayw = 2;
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/* Register memory range */
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/* Register memory range */
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register_memoryarea( gpio->baseaddr, GPIO_ADDR_SPACE, 4, 0, gpio_read32, gpio_write32, dat );
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reg_mem_area( gpio->baseaddr, GPIO_ADDR_SPACE, 0, &ops );
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reg_sim_reset(gpio_reset, dat);
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reg_sim_reset(gpio_reset, dat);
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reg_sim_stat(gpio_status, dat);
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reg_sim_stat(gpio_status, dat);
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}
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}
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