URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [peripheral/] [mc.c] - Diff between revs 1490 and 1519

Rev 1490	Rev 1519
Line 81...	Line 81...

`while (cur) {`	`while (cur) {`
`if (cur->cs == cs) {`	`if (cur->cs == cs) {`
`/* FIXME: No peripheral should _ever_ acess a dev_memarea structure`	`/* FIXME: No peripheral should _ever_ acess a dev_memarea structure`
`* directly */`	`* directly */`
	`TRACE("Remapping %"PRIxADDR"-%"PRIxADDR" to %"PRIxADDR"-%"PRIxADDR"\n",`
	`cur->mem->addr_compare,`
	`cur->mem->addr_compare \| cur->mem->size_mask,`
	`(csc >> MC_CSC_SEL_OFFSET) << 22,`
	`((csc >> MC_CSC_SEL_OFFSET) << 22) \| cur->mem->size_mask);`

`cur->mem->addr_mask = mc->ba_mask << 22;`	`cur->mem->addr_mask = mc->ba_mask << 22;`
`cur->mem->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;`	`cur->mem->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;`
`set_mem_valid(cur->mem, (csc >> MC_CSC_EN_OFFSET) & 0x01);`	`set_mem_valid(cur->mem, (csc >> MC_CSC_EN_OFFSET) & 0x01);`

`if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {`	`if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {`