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/* pic.c -- Simulation of OpenRISC 1000 programmable interrupt controller
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/* pic.c -- Simulation of OpenRISC 1000 programmable interrupt controller
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify it
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it under the terms of the GNU General Public License as published by
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under the terms of the GNU General Public License as published by the Free
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the Free Software Foundation; either version 2 of the License, or
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Software Foundation; either version 3 of the License, or (at your option)
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(at your option) any later version.
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* This is functional simulation of OpenRISC 1000 architectural
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This program is distributed in the hope that it will be useful, but WITHOUT
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programmable interrupt controller.
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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*/
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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#include <stdlib.h>
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You should have received a copy of the GNU General Public License along
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#include <stdio.h>
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <string.h>
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#include "config.h"
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#endif
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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#include <stdlib.h>
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#include <stdio.h>
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/* Package includes */
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "pic.h"
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#include "pic.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "spr-defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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DEFAULT_DEBUG_CHANNEL(pic);
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DEFAULT_DEBUG_CHANNEL(pic);
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/* FIXME: This ugly hack will be removed once the bus architecture gets written
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/* FIXME: This ugly hack will be removed once the bus architecture gets written
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*/
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*/
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struct pic pic_state_int = { 1, 1 };
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struct pic pic_state_int = { 1, 1 };
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struct pic *pic_state = &pic_state_int;
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struct pic *pic_state = &pic_state_int;
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/* Reset. It initializes PIC registers. */
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/* Reset. It initializes PIC registers. */
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void pic_reset(void)
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void
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pic_reset (void)
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{
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{
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PRINTF("Resetting PIC.\n");
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PRINTF("Resetting PIC.\n");
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cpu_state.sprs[SPR_PICMR] = 0;
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cpu_state.sprs[SPR_PICMR] = 0;
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cpu_state.sprs[SPR_PICPR] = 0;
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cpu_state.sprs[SPR_PICPR] = 0;
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cpu_state.sprs[SPR_PICSR] = 0;
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cpu_state.sprs[SPR_PICSR] = 0;
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}
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}
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/* Handles the reporting of an interrupt if it had to be delayed */
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/* Handles the reporting of an interrupt if it had to be delayed */
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static void pic_rep_int(void *dat)
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static void
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pic_rep_int (void *dat)
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{
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if (cpu_state.sprs[SPR_PICSR])
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{
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{
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if(cpu_state.sprs[SPR_PICSR]) {
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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}
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}
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}
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}
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/* Called whenever interrupts get enabled */
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/* Called whenever interrupts get enabled */
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void pic_ints_en(void)
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void
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pic_ints_en (void)
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{
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{
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if((cpu_state.sprs[SPR_PICMR] & cpu_state.sprs[SPR_PICSR]))
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if((cpu_state.sprs[SPR_PICMR] & cpu_state.sprs[SPR_PICSR]))
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SCHED_ADD(pic_rep_int, NULL, 0);
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SCHED_ADD(pic_rep_int, NULL, 0);
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}
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}
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/* Asserts interrupt to the PIC. */
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/* Asserts interrupt to the PIC. */
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/* WARNING: If this is called during a simulated instruction (ie. from a read/
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/* WARNING: If this is called during a simulated instruction (ie. from a read/
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* write mem callback), the interrupt will be delivered after the instruction
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* write mem callback), the interrupt will be delivered after the instruction
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* has finished executeing */
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* has finished executeing */
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void report_interrupt(int line)
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void
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report_interrupt (int line)
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{
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{
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uint32_t lmask = 1 << line;
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uint32_t lmask = 1 << line;
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/* Disable doze and sleep mode */
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/* Disable doze and sleep mode */
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cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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TRACE("Asserting interrupt %d (%s).\n", line,
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TRACE("Asserting interrupt %d (%s).\n", line,
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(cpu_state.sprs[SPR_PICMR] & lmask) ? "Unmasked" : "Masked");
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(cpu_state.sprs[SPR_PICMR] & lmask) ? "Unmasked" : "Masked");
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/* If PIC is disabled, don't set any register, just raise EXCEPT_INT */
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/* If PIC is disabled, don't set any register, just raise EXCEPT_INT */
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if(!pic_state->enabled) {
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if (!config.pic.enabled)
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{
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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return;
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return;
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}
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}
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if(cpu_state.pic_lines & lmask) {
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if (cpu_state.pic_lines & lmask)
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{
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/* No edge occured, warn about performance penalty and exit */
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/* No edge occured, warn about performance penalty and exit */
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WARN("Int line %d did not change state\n", line);
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WARN("Int line %d did not change state\n", line);
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return;
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return;
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}
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}
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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SCHED_ADD(pic_rep_int, NULL, 0);
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SCHED_ADD(pic_rep_int, NULL, 0);
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}
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}
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/* Clears an int on a pic line */
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/* Clears an int on a pic line */
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void clear_interrupt(int line)
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void
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clear_interrupt (int line)
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{
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{
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TRACE("Clearing interrupt %d\n", line);
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TRACE("Clearing interrupt %d\n", line);
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cpu_state.pic_lines &= ~(1 << line);
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cpu_state.pic_lines &= ~(1 << line);
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if(!pic_state->edge_trigger)
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if (!config.pic.edge_trigger)
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cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
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cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
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}
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}
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/*----------------------------------------------------[ PIC configuration ]---*/
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/*----------------------------------------------------[ PIC configuration ]---*/
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static void pic_enabled(union param_val val, void *dat)
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/*---------------------------------------------------------------------------*/
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/*!Enable or disable the programmable interrupt controller
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Set the corresponding field in the UPR
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@param[in] val The value to use
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@param[in] dat The config data structure (not used here) */
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/*---------------------------------------------------------------------------*/
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static void
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pic_enabled (union param_val val,
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void *dat)
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{
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if (val.int_val)
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{
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{
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struct pic *pic = dat;
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cpu_state.sprs[SPR_UPR] |= SPR_UPR_PICP;
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pic->enabled = val.int_val;
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}
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}
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else
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static void pic_edge_trigger(union param_val val, void *dat)
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{
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{
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struct pic *pic = dat;
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cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_PICP;
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pic->edge_trigger = val.int_val;
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}
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}
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static void *pic_start_sec(void)
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config.pic.enabled = val.int_val;
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} /* pic_enabled() */
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/*---------------------------------------------------------------------------*/
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/*!Enable or disable edge triggering of interrupts
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@param[in] val The value to use
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@param[in] dat The config data structure (not used here) */
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/*---------------------------------------------------------------------------*/
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static void
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pic_edge_trigger (union param_val val,
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void *dat)
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{
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{
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return pic_state;
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config.pic.edge_trigger = val.int_val;
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}
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} /* pic_edge_trigger() */
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void reg_pic_sec(void)
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/*---------------------------------------------------------------------------*/
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/*!Initialize a new interrupt controller configuration
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ALL parameters are set explicitly to default values in init_defconfig() */
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/*---------------------------------------------------------------------------*/
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void
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reg_pic_sec ()
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{
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{
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struct config_section *sec = reg_config_sec("pic", pic_start_sec, NULL);
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struct config_section *sec = reg_config_sec ("pic", NULL, NULL);
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reg_config_param(sec, "enabled", paramt_int, pic_enabled);
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reg_config_param(sec, "enabled", paramt_int, pic_enabled);
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reg_config_param(sec, "edge_trigger", paramt_int, pic_edge_trigger);
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reg_config_param(sec, "edge_trigger", paramt_int, pic_edge_trigger);
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}
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} /* reg_pic_sec() */
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