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/* sim-config.c -- Simulator configuration
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/* sim-config.c -- Simulator configuration
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify it
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it under the terms of the GNU General Public License as published by
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under the terms of the GNU General Public License as published by the Free
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the Free Software Foundation; either version 2 of the License, or
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Software Foundation; either version 3 of the License, or (at your option)
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(at your option) any later version.
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any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful, but WITHOUT
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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GNU General Public License for more details.
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more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License along
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along with this program; if not, write to the Free Software
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Simulator configuration. Eventually this one will be a lot bigger. */
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/* Simulator configuration. Eventually this one will be a lot bigger. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <limits.h>
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#include <limits.h>
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config.cpu.superscalar = 0;
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config.cpu.superscalar = 0;
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config.sim.history = 0;
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config.sim.history = 0;
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config.cpu.hazards = 0;
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config.cpu.hazards = 0;
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config.cpu.dependstats = 0;
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config.cpu.dependstats = 0;
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config.cpu.sbuf_len = 0;
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config.cpu.sbuf_len = 0;
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config.cpu.upr = SPR_UPR_UP | SPR_UPR_DCP | SPR_UPR_ICP | SPR_UPR_DMP
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config.cpu.upr = SPR_UPR_UP | SPR_UPR_DCP | SPR_UPR_ICP | SPR_UPR_DMP |
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| SPR_UPR_IMP | SPR_UPR_OB32P | SPR_UPR_DUP | SPR_UPR_PICP
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SPR_UPR_IMP | SPR_UPR_DUP | SPR_UPR_PMP | SPR_UPR_PICP |
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| SPR_UPR_PMP | SPR_UPR_TTP;
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SPR_UPR_TTP;
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config.cpu.sr = 0x00008001;
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config.cpu.cfgr = SPR_CPUCFGR_OB32S;
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config.cpu.sr = SPR_SR_FO | SPR_SR_SM;
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/* Debug */
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/* Debug */
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config.debug.enabled = 0;
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config.debug.enabled = 0;
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config.debug.gdb_enabled = 0;
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config.debug.gdb_enabled = 0;
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config.debug.server_port = 0;
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config.debug.server_port = 0;
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config.debug.cfgr = SPR_DCFGR_WPCI | /* JPB */
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MATCHPOINTS_TO_NDP( MAX_MATCHPOINTS );
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/* VAPI */
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/* VAPI */
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config.vapi.enabled = 0;
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config.vapi.enabled = 0;
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strcpy (config.vapi.vapi_fn, "vapi.log");
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strcpy (config.vapi.vapi_fn, "vapi.log");
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PRINTF ("Invalid parameters specified.\n");
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PRINTF ("Invalid parameters specified.\n");
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break;
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break;
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}
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}
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}
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}
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