Line 1... |
Line 1... |
This directory includes some test case programs that should be used to verify correct operation
|
Or1ksim Test Suite
|
of the or1ksim, OR32 GCC and OR32 GNU Binutils.
|
==================
|
|
|
All programs are built and checked by:
|
|
|
|
./configure --target=or32-uclinux
|
This directory includes some test case programs that should be used to verify
|
make all check
|
correct operation of the or1ksim, OR32 GCC and OR32 GNU Binutils.
|
|
|
You need to have all GNU OR32 tools installed and in the path.
|
|
|
|
!!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE undefined in
|
Pre-requisites
|
cpu/or1k/except.h !!!
|
==============
|
|
|
|
The GNU toolchain for OpenRISC 1000 is required. Instructions how to build
|
|
these GNU tools can be found on www.opencores.org
|
|
|
|
Or1ksim must be built and installed (see ../README)
|
|
|
|
|
|
Configuration and Running
|
|
=========================
|
|
|
|
The installation uses standard GNU autoconf/automake files. Generic
|
|
instructions on this are in the INSTALL file.
|
|
|
|
Or1ksim Test Suite should be capable of being built in a separate directory -
|
|
but for now that is broken.
|
|
|
|
All programs are built and checked from the test directory by:
|
|
|
|
$ ./configure --target=or32-uclinux --host=or32
|
|
$ make all
|
|
$ make check
|
|
|
|
|
|
!!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE !!!
|
|
!!! undefined in cpu/or1k/except.h. This is the default behavior !!!
|
|
|
All tests should exit with:
|
All tests should exit with:
|
|
|
MTSPR(0x1234, deaddead);
|
MTSPR(0x1234, deaddead);
|
syscall exit(0)
|
syscall exit(0)
|
|
|
If the test fails, it should print as much output as possible about the failure.
|
If the test fails, it should print as much output as possible about the
|
|
failure. Overall the test script checks for the above two lines, and can be
|
|
fooled by intervening log output.
|
|
|
|
|
dhry: Dhrystone 2.1: a benchmark modified to use simulator's timing facility.
|
The Tests
|
|
=========
|
|
|
|
A total of 20 tests including:
|
|
|
|
dhry: Dhrystone 2.1: a benchmark modified to use simulator's timing
|
|
facility.
|
basic: a test for all instructions and all GPRs.
|
basic: a test for all instructions and all GPRs.
|
test1: a test for "all" instructions and their combinations.
|
test1: a test for "all" instructions and their combinations.
|
pic: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC.
|
pic: a test for PIC and TICK timer. All three modes of TICK timer are
|
excpt: a test of l.sys instruction. Checks all the delay slot issues ind other things.
|
tested and interrupt is enabled and disabled in PIC.
|
cfg: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR).
|
excpt: a test of l.sys instruction. Checks all the delay slot issues ind
|
|
other things.
|
|
cfg: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR,
|
|
SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR).
|
dma: a test of DMA in normal (software) mode.
|
dma: a test of DMA in normal (software) mode.
|
compress: UNIX compressed modified not to use libc calls.
|
compress: UNIX compressed modified not to use libc calls.
|
mul: Test l.mul, l.mac and l.macrc instructions.
|
mul: Test l.mul, l.mac and l.macrc instructions.
|
|
|
|
|
|
Upated by Jeremy Bennett (jeremy@jeremybennett.com)
|
|
9 June 2008
|