| Line 80... |
Line 80... |
ASSERT(getreg (UART_IER) == 0x00); //1
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ASSERT(getreg (UART_IER) == 0x00); //1
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ASSERT(getreg (UART_IIR) == 0xc1); //2
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ASSERT(getreg (UART_IIR) == 0xc1); //2
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ASSERT(getreg (UART_LCR) == 0x03); //3
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ASSERT(getreg (UART_LCR) == 0x03); //3
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ASSERT(getreg (UART_MCR) == 0x00); //4
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ASSERT(getreg (UART_MCR) == 0x00); //4
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ASSERT(getreg (UART_LSR) == 0x60); //5
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ASSERT(getreg (UART_LSR) == 0x60); //5
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ASSERT(getreg (UART_MSR) == 0x00); //6
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// ASSERT(getreg (UART_MSR) == 0xff); //6
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// ASSERT(getreg (UART_MSR) == 0x00); //6
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setreg(UART_LCR, LCR_DIVL); //enable latches
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setreg(UART_LCR, LCR_DIVL); //enable latches
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLL) == 0x00); //0
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ASSERT(getreg (UART_DLH) == 0x00); //1
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ASSERT(getreg (UART_DLH) == 0x00); //1
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setreg(UART_LCR, 0x00); //disable latches
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setreg(UART_LCR, 0x00); //disable latches
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| Line 96... |
Line 97... |
tmp = getreg (UART_LSR);
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tmp = getreg (UART_LSR);
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setreg (UART_LSR, ~tmp);
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setreg (UART_LSR, ~tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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for (i = 0; i < 9; i++) {
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for (i = 0; i < 9; i++) {
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setreg (UART_LSR, 1 < i);
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setreg (UART_LSR, 1 << i);
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ASSERT(getreg (UART_LSR) == tmp);
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ASSERT(getreg (UART_LSR) == tmp);
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}
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}
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tmp = getreg (UART_MSR);
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/*tmp = getreg (UART_MSR);
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setreg (UART_MSR, ~tmp);
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setreg (UART_MSR, ~tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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for (i = 0; i < 9; i++) {
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for (i = 0; i < 9; i++) {
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setreg (UART_MSR, 1 < i);
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setreg (UART_MSR, 1 << i);
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ASSERT(getreg (UART_MSR) == tmp);
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ASSERT(getreg (UART_MSR) == tmp);
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}
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}*/
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}
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}
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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{ /* test whether MCR is write only, be careful not to set the loopback bit */
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{ /* test whether MCR is write only, be careful not to set the loopback bit */
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ASSERT(getreg (UART_MCR) == 0x00);
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/*ASSERT(getreg (UART_MCR) == 0x00);
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setreg (UART_MCR, 0x45);
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setreg (UART_MCR, 0x45);
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ASSERT(getreg (UART_MCR) == 0x00);
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ASSERT(getreg (UART_MCR) == 0x00);
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setreg (UART_MCR, 0xaa);
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setreg (UART_MCR, 0xaa);
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ASSERT(getreg (UART_MCR) == 0x00);
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ASSERT(getreg (UART_MCR) == 0x00);*/
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}
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}
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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ASSERT (!(getreg (UART_LSR) & 0x1f));
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{ /* Test if Divisor latch byte holds the data */
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{ /* Test if Divisor latch byte holds the data */
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int i;
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int i;
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setreg(UART_LCR, LCR_DIVL); //enable latches
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setreg(UART_LCR, LCR_DIVL); //enable latches
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| Line 182... |
Line 183... |
/* Wait for tx fifo to be empty */
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/* Wait for tx fifo to be empty */
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while (!(getreg (UART_LSR) & LSR_TXFE));
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while (!(getreg (UART_LSR) & LSR_TXFE));
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NO_ERROR();
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NO_ERROR();
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setreg (UART_THR, *s); /* send character */
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setreg (UART_THR, *s); /* send character */
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NO_ERROR();
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NO_ERROR();
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report((unsigned long)*s);
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s++;
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s++;
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}
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}
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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ASSERT (!(getreg (UART_LSR) & LSR_DR));
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s = "test_";
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s = "test_";
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while (*s) {
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while (*s) {
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| Line 205... |
Line 207... |
/* Wait for tx fifo and tx to be empty */
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/* Wait for tx fifo and tx to be empty */
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while (!(getreg (UART_LSR) & LSR_TXE));
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while (!(getreg (UART_LSR) & LSR_TXE));
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NO_ERROR();
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NO_ERROR();
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setreg (UART_THR, *s); /* send character */
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setreg (UART_THR, *s); /* send character */
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NO_ERROR();
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NO_ERROR();
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for (i = 0; i < 1600; i++) /* wait at least ten chars before sending next one */
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// igor for (i = 0; i < 1600; i++) /* wait at least ten chars before sending next one */
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for (i = 0; i < 16; i++) /* wait at least ten chars before sending next one */
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asm volatile ("l.nop");
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asm volatile ("l.nop");
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s++;
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s++;
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}
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}
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while (!(getreg (UART_LSR) & LSR_TXE));
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while (!(getreg (UART_LSR) & LSR_TXE));
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