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[/] [or1k/] [trunk/] [or1ksim/] [testbench/] [acv_uart.c] - Diff between revs 376 and 380

Rev 376	Rev 380
Line 80...	Line 80...
`ASSERT(getreg (UART_RBR) == 0x00); //0`	`ASSERT(getreg (UART_RBR) == 0x00); //0`
`ASSERT(getreg (UART_IER) == 0x00); //1`	`ASSERT(getreg (UART_IER) == 0x00); //1`
`ASSERT(getreg (UART_IIR) == 0xc1); //2`	`ASSERT(getreg (UART_IIR) == 0xc1); //2`
`ASSERT(getreg (UART_LCR) == 0x03); //3`	`ASSERT(getreg (UART_LCR) == 0x03); //3`
`ASSERT(getreg (UART_MCR) == 0x00); //4`	`ASSERT(getreg (UART_MCR) == 0x00); //4`
`ASSERT(getreg (UART_LSR) == 0x60); //5`	`// ASSERT(getreg (UART_LSR) == 0x60); //5`
`// ASSERT(getreg (UART_MSR) == 0xff); //6`	`// ASSERT(getreg (UART_MSR) == 0xff); //6`
`// ASSERT(getreg (UART_MSR) == 0x00); //6`	`ASSERT(getreg (UART_MSR) == 0x00); //6`

`setreg(UART_LCR, LCR_DIVL); //enable latches`	`setreg(UART_LCR, LCR_DIVL); //enable latches`
`ASSERT(getreg (UART_DLL) == 0x00); //0`	`ASSERT(getreg (UART_DLL) == 0x00); //0`
`ASSERT(getreg (UART_DLH) == 0x00); //1`	`ASSERT(getreg (UART_DLH) == 0x00); //1`
`setreg(UART_LCR, 0x00); //disable latches`	`setreg(UART_LCR, 0x00); //disable latches`