| Line 53... |
Line 53... |
/* Exception vectors */
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/* Exception vectors */
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#define V_RESET 1
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#define V_RESET 1
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#define V_BERR 2
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#define V_BERR 2
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#define V_DPF 3
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#define V_DPF 3
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#define V_IPF 4
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#define V_IPF 4
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#define V_LPINT 5
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#define V_TICK 5
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#define V_ALIGN 6
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#define V_ALIGN 6
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#define V_ILLINSN 7
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#define V_ILLINSN 7
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#define V_HPINT 8
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#define V_INT 8
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#define V_DTLB_MISS 9
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#define V_DTLB_MISS 9
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#define V_ITLB_MISS 10
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#define V_ITLB_MISS 10
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#define V_RANGE 11
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#define V_RANGE 11
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#define V_SYS 12
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#define V_SYS 12
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#define V_TRAP 14
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#define V_TRAP 14
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| Line 154... |
Line 154... |
except_mask |= 1 << V_ILLINSN;
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except_mask |= 1 << V_ILLINSN;
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except_count++;
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except_count++;
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}
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}
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/* Low priority interrupt handler */
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/* Low priority interrupt handler */
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void lp_int_handler (void)
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void tick_handler (void)
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{
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{
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|
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/* Disable interrupt recognition */
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/* Disable interrupt recognition */
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mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_EIR);
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mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_TEE);
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except_mask |= 1 << V_LPINT;
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except_mask |= 1 << V_TICK;
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except_count++;
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except_count++;
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}
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}
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/* High priority interrupt handler */
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/* High priority interrupt handler */
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void hp_int_handler (void)
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void int_handler (void)
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{
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{
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|
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/* Disable interrupt recognition */
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/* Disable interrupt recognition */
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mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_EIR);
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mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_IEE);
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except_mask |= 1 << V_HPINT;
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except_mask |= 1 << V_INT;
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except_count++;
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except_count++;
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}
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}
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/* Trap handler */
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/* Trap handler */
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void trap_handler (void)
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void trap_handler (void)
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| Line 333... |
Line 333... |
}
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}
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/* Tick timer init */
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/* Tick timer init */
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void tick_init (int period, int hp_int)
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void tick_init (int period, int hp_int)
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{
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{
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/* Disable interrupt recognition */
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/* Disable tick timer exception recognition */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_TEE);
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|
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/* Set period of one cycle, restartable mode */
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/* Set period of one cycle, restartable mode */
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mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (period & SPR_TTMR_PERIOD));
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mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (period & SPR_TTMR_PERIOD));
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/* Set tick priority */
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if (hp_int)
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mtspr(SPR_PICPR, mfspr(SPR_PICPR) | (0x00000001L << V_TICK));
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else
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mtspr(SPR_PICPR, mfspr(SPR_PICPR) & ~(0x00000001L << V_TICK));
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/* Reset counter */
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/* Reset counter */
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mtspr(SPR_TTCR, 0);
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mtspr(SPR_TTCR, 0);
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|
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/* Unmask tick interrupt in PIC */
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << V_TICK));
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}
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}
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/* Interrupt test */
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/* Interrupt test */
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int interrupt_test (void)
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int interrupt_test (void)
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{
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{
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| Line 370... |
Line 361... |
except_ea = 0;
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except_ea = 0;
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|
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/* Test normal high priority interrupt trigger */
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/* Test normal high priority interrupt trigger */
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ret = call ((unsigned long)&int_trigger, 0);
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ret = call ((unsigned long)&int_trigger, 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_HPINT));
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ASSERT(except_mask == (1 << V_TICK));
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ASSERT(ret == 0);
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ASSERT(except_pc == (unsigned long)int_trigger + 16);
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#if 0
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/* Reset except counter */
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except_count = 0;
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except_mask = 0;
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except_pc = 0;
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except_ea = 0;
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/* Init tick timer */
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tick_init (1, 0);
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|
|
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/* Test normal low priority interrupt trigger */
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ret = call ((unsigned long)&int_trigger, 0);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_LPINT));
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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ASSERT(except_pc == (unsigned long)int_trigger + 16);
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ASSERT(except_pc == (unsigned long)int_trigger + 16);
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ASSERT(except_ea == 0);
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#endif
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|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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| Line 949... |
Line 921... |
immu_enable ();
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immu_enable ();
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|
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/* Check if there was INT exception */
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/* Check if there was INT exception */
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call_with_int (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
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call_with_int (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_HPINT));
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ASSERT(except_mask == (1 << V_TICK));
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ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
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ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
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ASSERT(except_ea == 0);
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ASSERT(except_ea == 0);
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|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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| Line 1118... |
Line 1090... |
excpt_buserr = (unsigned long)bus_err_handler;
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excpt_buserr = (unsigned long)bus_err_handler;
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|
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/* Register illegal insn handler */
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/* Register illegal insn handler */
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excpt_illinsn = (unsigned long)ill_insn_handler;
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excpt_illinsn = (unsigned long)ill_insn_handler;
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|
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/* Register low priority interrupt handler */
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/* Register tick timer exception handler */
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excpt_lpint = (unsigned long)lp_int_handler;
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excpt_tick = (unsigned long)tick_handler;
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|
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/* Register high priority interrupt handler */
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/* Register external interrupt handler */
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excpt_hpint = (unsigned long)hp_int_handler;
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excpt_int = (unsigned long)int_handler;
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|
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/* Register ITLB miss handler */
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/* Register ITLB miss handler */
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excpt_itlbmiss = (unsigned long)itlb_miss_handler;
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excpt_itlbmiss = (unsigned long)itlb_miss_handler;
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|
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/* Register instruction page fault handler */
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/* Register instruction page fault handler */
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