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https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [trunk/] [or1ksim/] [toplevel.c] - Diff between revs 1689 and 1690
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Rev 1689 |
Rev 1690 |
Line 340... |
Line 340... |
runtime.sim.hush = 1;
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runtime.sim.hush = 1;
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recalc_do_stats();
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recalc_do_stats();
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sim_init ();
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sim_init ();
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while(1) {
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exec_main();
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long long time_start = runtime.sim.cycles;
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if (config.debug.enabled) {
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du_clock(); // reset watchpoints
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while (runtime.cpu.stalled) {
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if(config.debug.gdb_enabled) {
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BlockJTAG();
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HandleServerSocket(false);
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} else {
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fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.\n");
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/* Dump the user into interactive mode. From there he can decide what
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* to do. */
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handle_sim_command();
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sim_done();
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}
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if(runtime.sim.iprompt)
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handle_sim_command();
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}
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}
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/* Each cycle has counter of mem_cycles; this value is joined with cycles
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at the end of the cycle; no sim originated memory accesses should be
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performed inbetween. */
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runtime.sim.mem_cycles = 0;
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if (!config.pm.enabled ||
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!(cpu_state.sprs[SPR_PMR] & (SPR_PMR_DME | SPR_PMR_SME)))
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if (cpu_clock ())
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/* A breakpoint has been hit, drop to interactive mode */
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handle_sim_command();
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if (config.vapi.enabled && runtime.vapi.enabled) vapi_check();
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if (config.debug.gdb_enabled) HandleServerSocket(false); /* block & check_stdin = false */
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if(config.debug.enabled)
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if (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST) set_stall_state (1);
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runtime.sim.cycles += runtime.sim.mem_cycles;
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scheduler.job_queue->time -= runtime.sim.cycles - time_start;
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if (scheduler.job_queue->time <= 0) do_scheduler ();
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}
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sim_done();
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sim_done();
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}
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}
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