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| Rev 1052 |
Rev 1193 |
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Line 44... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/09/16 02:51:23 lampret
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// Delayed wb_err_o. Disabled wb_ack_o when wb_err_o is asserted.
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//
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// Revision 1.4 2002/08/18 19:55:30 lampret
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// Revision 1.4 2002/08/18 19:55:30 lampret
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// Added variable delay for SRAM.
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// Added variable delay for SRAM.
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//
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//
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// Revision 1.3 2002/08/14 06:24:43 lampret
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// Revision 1.3 2002/08/14 06:24:43 lampret
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// Fixed size of generic flash/sram to exactly 2MB
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// Fixed size of generic flash/sram to exactly 2MB
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Line 75... |
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`define SRAM_GENERIC
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//
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// Disable SRAM_GENERIC when using FPGAs
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//
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//`define SRAM_GENERIC
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`ifdef SRAM_GENERIC
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`ifdef SRAM_GENERIC
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module sram_top (
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module sram_top (
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wb_clk_i, wb_rst_i,
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wb_clk_i, wb_rst_i,
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Line 347... |
assign r_d_o = r_mux;
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assign r_d_o = r_mux;
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assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
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assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
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assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
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assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
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assign l_cen = ~(wb_cyc_i & wb_stb_i);
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assign l_cen = ~(wb_cyc_i & wb_stb_i);
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assign r_cen = l_cen;
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assign r_cen = l_cen;
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assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_err & ~wb_we_i) | ack_we;
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assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i) | ack_we;
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assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored)
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assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored)
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//
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//
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// RMW mux control
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// RMW mux control
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//
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//
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