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// Revision 1.1.1.1  2002/03/21 16:55:44  lampret

// First import of the "new" XESS XSV environment.

//

//

`define SRAM_GENERIC

`ifdef SRAM_GENERIC

module sram_top (

  wb_clk_i, wb_rst_i,

  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,

  wb_stb_i, wb_ack_o, wb_err_o,

  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,

  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o

);

//

// Paraneters

//

parameter               aw = 19;

//

// I/O Ports

//

input                   wb_clk_i;

input                   wb_rst_i;

//

// WB slave i/f

//

input   [31:0]           wb_dat_i;

output  [31:0]           wb_dat_o;

input   [31:0]           wb_adr_i;

input   [3:0]            wb_sel_i;

input                   wb_we_i;

input                   wb_cyc_i;

input                   wb_stb_i;

output                  wb_ack_o;

output                  wb_err_o;

//

// Right SRAM bank

//

output                  r_oen;

output                  r0_wen;

output                  r1_wen;

output                  r_cen;

input   [15:0]           r_d_i;

output  [15:0]           r_d_o;

output  [aw-1:0] r_a;

//

// Left SRAM bank

//

output                  l_oen;

output                  l0_wen;

output                  l1_wen;

output                  l_cen;

input   [15:0]           l_d_i;

output  [15:0]           l_d_o;

output  [aw-1:0] l_a;

//

// Common SRAM signals

//

output                  d_oe;

//

// Internal wires and regs

//

reg     [7:0]           mem [2100000:0];

wire    [31:0]          adr;

`ifdef SRAM_GENERIC_REGISTERED

reg                     wb_ack_o;

reg                     wb_err_o;

reg     [31:0]          wb_dat_o;

`endif

wire                    wb_err;

//

// Aliases and simple assignments

//

assign wb_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:21]);     // If Access to > 2MB (8-bit leading prefix ignored)

assign adr = {8'h00, wb_adr_i[23:2], 2'b00};

`ifdef SRAM_GENERIC_REGISTERED

//

// Reading from SRAM model

//

always @(posedge wb_rst_i or posedge wb_clk_i)

        if (wb_rst_i)

                wb_dat_o <= #1 32'h0000_0000;

        else begin

                wb_dat_o[7:0] <= #1 mem[adr+3];

                wb_dat_o[15:8] <= #1 mem[adr+2];

                wb_dat_o[23:16] <= #1 mem[adr+1];

                wb_dat_o[31:24] <= #1 mem[adr+0];

        end

`else

assign wb_dat_o[7:0] = mem[adr+3];

assign wb_dat_o[15:8] = mem[adr+2];

assign wb_dat_o[23:16] = mem[adr+1];

assign wb_dat_o[31:24] = mem[adr+0];

`endif

//

// Writing to SRAM model

//

always @(posedge wb_rst_i or posedge wb_clk_i)

        if (wb_cyc_i & wb_stb_i & wb_we_i) begin

                if (wb_sel_i[0])

                        mem[adr+3] <= #1 wb_dat_i[7:0];

                if (wb_sel_i[1])

                        mem[adr+2] <= #1 wb_dat_i[15:8];

                if (wb_sel_i[2])

                        mem[adr+1] <= #1 wb_dat_i[23:16];

                if (wb_sel_i[3])

                        mem[adr+0] <= #1 wb_dat_i[31:24];

        end

`ifdef SRAM_GENERIC_REGISTERED

//

// WB Acknowledge

//

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

                wb_ack_o <= #1 1'b0;

        else

                wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;

`else

assign wb_ack_o = wb_cyc_i & wb_stb_i;

`endif

`ifdef SRAM_GENERIC_REGISTERED

//

// WB Error

//

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

                wb_err_o <= #1 1'b0;

        else

                wb_err_o <= #1 wb_err & !wb_err_o;

`else

assign wb_err_o = wb_err;

`endif

//

// Flash i/f monitor

//

// synopsys translate_off

integer fsram;

initial fsram = $fopen("sram.log");

always @(posedge wb_clk_i)

        if (wb_cyc_i)

                if (wb_stb_i & wb_we_i) begin

                        if (wb_sel_i[3])

                                mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];

                        if (wb_sel_i[2])

                                mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];

                        if (wb_sel_i[1])

                                mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];

                        if (wb_sel_i[0])

                                mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];

                        $fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);

                end else if (wb_ack_o)

                        $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);

// synopsys translate_on

endmodule

`else

`endif