URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orpmon/] [sim.cfg] - Diff between revs 987 and 1495

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 987	Rev 1495
Line 1...	Line 1...
`/* sim.cfg -- Simulator configuration script file`	`/* sim.cfg -- Simulator configuration script file`
`Copyright (C) 2001, Marko Mlinar, markom@opencores.org`	`Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org`

`This file is part of OpenRISC 1000 Architectural Simulator.`	`This file is part of OpenRISC 1000 Architectural Simulator.`
`It contains the default configuration and help about configuring`	`It contains the default configuration and help about configuring`
`the simulator.`	`the simulator.`

Line 372...	Line 372...
`clkcycle = [ps\|ns\|us\|ms]`	`clkcycle = [ps\|ns\|us\|ms]`
`specifies time measurement for one cycle`	`specifies time measurement for one cycle`
`*/`	`*/`

`section sim`	`section sim`
`verbose = 0`	`/* verbose = 1 */`
`debug = 0`	`debug = 0`
`profile = 0`	`profile = 0`
`prof_fn = "sim.profile"`	`prof_fn = "sim.profile"`

`history = 1`	`history = 1`
Line 457...	Line 457...
`'0': don't calculate inter-instruction dependencies.`	`'0': don't calculate inter-instruction dependencies.`
`'1': calculate inter-instruction dependencies.`	`'1': calculate inter-instruction dependencies.`
`If calculated, inter-instruction dependencies can be`	`If calculated, inter-instruction dependencies can be`
`displayed using the simulator's 'stat' command.`	`displayed using the simulator's 'stat' command.`

`raw_range =`
`range in cycles for raw register over time analysis, 0 = disabled`

`sbuf_len =`	`sbuf_len =`
`length of store buffer (<= 256), 0 = disabled`	`length of store buffer (<= 256), 0 = disabled`
`*/`	`*/`

`section cpu`	`section cpu`
Line 471...	Line 468...
`rev = 0x0001`	`rev = 0x0001`
`/* upr = */`	`/* upr = */`
`superscalar = 0`	`superscalar = 0`
`hazards = 0`	`hazards = 0`
`dependstats = 0`	`dependstats = 0`
	`sbuf_len = 0`
`end`	`end`


`/* PM SECTION`	`/* PM SECTION`

Line 570...	Line 568...
`POC =`	`POC =`
`Power On Configuration register`	`Power On Configuration register`
`*/`	`*/`

`section mc`	`section mc`
`enabled = 1`	`enabled = 0`
`baseaddr = 0x93000000`	`baseaddr = 0x93000000`
`POC = 0x00000008 /* Power on configuration register */`	`POC = 0x00000008 /* Power on configuration register */`
`end`	`end`


`/* UART SECTION`	`/* UART SECTION`

`This section configures the UARTs`	`This section configures the UARTs`

`nuarts =`	`enabled = <0\|1>`
`make specified number of instances, configure each`	`Enable/disable the peripheral. By default if it is enabled.`
`instance within device - enddevice construct.`

`instance specific:`
`baseaddr =`	`baseaddr =`
`address of first UART register for this device`	`address of first UART register for this device`

`rxfile = ""`
`filename, where to read data from`

`txfile = ""`	`channel = :`
`filename, where to write data to`
	`The channel parameter indicates the source of received UART characters`
	`and the sink for transmitted UART characters.`

	`The can be either "file", "xterm", "tcp", "fd", or "tty"`
	`(without quotes).`

	`A) To send/receive characters from a pair of files, use a file`
	`channel:`

	`channel=file:,`

	`B) To create an interactive terminal window, use an xterm channel:`

	`channel=xterm:[]*`

	`C) To create a bidirectional tcp socket which one could, for example,`
	`access via telnet, use a tcp channel:`

	`channel=tcp:`

	`D) To cause the UART to read/write from existing numeric file`
	`descriptors, use an fd channel:`

	`channel=fd:,`

	`E) To connect the UART to a physical serial port, create a tty`
	`channel:`

	`channel=tty:device=/dev/ttyS0,baud=9600`

`irq =`	`irq =`
`irq number for this device`	`irq number for this device`

`16550 = 0/1`	`16550 = 0/1`
Line 609...	Line 632...
`vapi_id =`	`vapi_id =`
`VAPI id of this instance`	`VAPI id of this instance`
`*/`	`*/`

`section uart`	`section uart`
`nuarts = 1`	`enabled = 1`

`device 0`
`baseaddr = 0x90000000`	`baseaddr = 0x90000000`
`irq = 2`	`irq = 2`
`rxfile = "uart0.rx"`	`channel = "file:uart0.rx,uart0.tx"`
`txfile = "uart0.tx"`
`jitter = -1 /* async behaviour */`	`jitter = -1 /* async behaviour */`
`16550 = 1`	`16550 = 1`
`enddevice`
`end`	`end`


`/* DMA SECTION`	`/* DMA SECTION`

`This section configures the DMAs`	`This section configures the DMAs`

`ndmas =`	`enabled = <0\|1>`
`make specified number of instances, configure each`	`Enable/disable the peripheral. By default if it is enabled.`
`instance within device - enddevice construct.`

`instance specific:`
`baseaddr =`	`baseaddr =`
`address of first DMA register for this device`	`address of first DMA register for this device`

`irq =`	`irq =`
`irq number for this device`	`irq number for this device`
Line 642...	Line 659...
`vapi_id =`	`vapi_id =`
`VAPI id of this instance`	`VAPI id of this instance`
`*/`	`*/`

`section dma`	`section dma`
`ndmas = 0`	`enabled = 1`

`/*`
`device 0`
`baseaddr = 0x9a000000`	`baseaddr = 0x9a000000`
`irq = 11`	`irq = 11`
`enddevice`
`*/`
`end`	`end`


`/* ETHERNET SECTION`	`/* ETHERNET SECTION`

`This section configures the ETHERNETs`	`This section configures the ETHERNETs`

`nethernets =`	`enabled = <0\|1>`
`make specified number of instances, configure each`	`Enable/disable the peripheral. By default if it is enabled.`
`instance within device - enddevice construct.`

`instance specific:`
`baseaddr =`	`baseaddr =`
`address of first ethernet register for this device`	`address of first ethernet register for this device`

`dma =`	`dma =`
`which controller is this ethernet "connected" to`	`which controller is this ethernet "connected" to`
Line 694...	Line 704...
`vapi_id =`	`vapi_id =`
`VAPI id of this instance`	`VAPI id of this instance`
`*/`	`*/`

`section ethernet`	`section ethernet`
`nethernets = 1`

`device 0`
`baseaddr = 0x92000000`	`baseaddr = 0x92000000`
`dma = 0`	`dma = 0`
`irq = 4`	`irq = 4`
`rtx_type = 1`	`rtx_type = 0`
`tx_channel = 0`	`tx_channel = 0`
`rx_channel = 1`	`rx_channel = 1`
`rxfile = "eth0.rx"`	`rxfile = "eth0.rx"`
`txfile = "eth0.tx"`	`txfile = "eth0.tx"`
`sockif = "eth0"`	`sockif = "eth0"`
`enddevice`
`end`	`end`


`/* GPIO SECTION`	`/* GPIO SECTION`

`This section configures the GPIOs`	`This section configures the GPIOs`

`ngpios =`	`enabled = <0\|1>`
`make specified number of instances, configure each`	`Enable/disable the peripheral. By default if it is enabled.`
`instance within device - enddevice construct.`

`instance specific:`
`baseaddr =`	`baseaddr =`
`address of first GPIO register for this device`	`address of first GPIO register for this device`

`irq =`	`irq =`
`irq number for this device`	`irq number for this device`
Line 731...	Line 735...
`first VAPI id of this instance`	`first VAPI id of this instance`
`GPIO uses 8 consecutive VAPI IDs`	`GPIO uses 8 consecutive VAPI IDs`
`*/`	`*/`

`section gpio`	`section gpio`
`ngpios = 1`	`enabled = 1`

`device 0`
`baseaddr = 0x91000000`	`baseaddr = 0x91000000`
`irq = 3`	`irq = 3`
`base_vapi_id = 0x0200`	`base_vapi_id = 0x0200`
`enddevice`
`end`	`end`

`/* VGA SECTION`	`/* VGA SECTION`

`This section configures the VGA/LCD controller`	`This section configures the VGA/LCD controller`

`nvgas =`	`enabled = <0\|1>`
`number of VGA devices connected`	`Enable/disable the peripheral. By default if it is enabled.`

`instance specific:`
`baseaddr =`	`baseaddr =`
`address of first VGA register`	`address of first VGA register`

`irq =`	`irq =`
`irq number for this device`	`irq number for this device`
Line 762...	Line 762...
`filename = ""`	`filename = ""`
`template name for generated names (e.g. "primary" produces "primary0023.bmp")`	`template name for generated names (e.g. "primary" produces "primary0023.bmp")`
`*/`	`*/`

`section vga`	`section vga`
`nvgas = 1`	`enabled = 1`

`device 0`
`baseaddr = 0x97100000`	`baseaddr = 0x97100000`
`irq = 8`	`irq = 8`
`refresh_rate = 100000`	`refresh_rate = 100000`
`filename = "primary"`	`filename = "primary"`
`enddevice`
`end`	`end`


`/* TICK TIMER SECTION`	`/* TICK TIMER SECTION`

Line 794...	Line 791...

`/* FB SECTION`	`/* FB SECTION`

`This section configures the frame buffer`	`This section configures the frame buffer`

`enabled = 0/1`	`enabled = <0\|1>`
`whether frame buffer is enabled`	`Enable/disable the peripheral. By default if it is enabled.`

`baseaddr =`	`baseaddr =`
`base address of frame buffer`	`base address of frame buffer`

`paladdr =`	`paladdr =`
Line 822...	Line 819...

`/* KBD SECTION`	`/* KBD SECTION`

`This section configures the PS/2 compatible keyboard`	`This section configures the PS/2 compatible keyboard`

`enabled = 0/1`
`whether keyboard is enabled`

`baseaddr =`	`baseaddr =`
`base address of the keyboard device`	`base address of the keyboard device`

`rxfile = ""`	`rxfile = ""`
`filename, where to read data from`	`filename, where to read data from`
Line 844...	Line 838...

`/* ATA SECTION`	`/* ATA SECTION`

`This section configures the ATA/ATAPI host controller`	`This section configures the ATA/ATAPI host controller`

`natas =`
`number of ATA hosts connected`

`instance specific:`
`baseaddr =`	`baseaddr =`
`address of first ATA register`	`address of first ATA register`

	`enabled = <0\|1>`
	`Enable/disable the peripheral. By default if it is enabled.`

`irq =`	`irq =`
`irq number for this device`	`irq number for this device`

`debug =`	`debug =`
`debug level for ata models.`	`debug level for ata models.`
Line 885...	Line 878...

`FIXME: irq number`	`FIXME: irq number`
`*/`	`*/`

`section ata`	`section ata`
`natas = 1`	`enabled = 1`

`device 0`
`baseaddr = 0x9e000000`	`baseaddr = 0x9e000000`
`irq = 15`	`irq = 15`

`dev_type0 = 1`	`dev_type0 = 1`
`dev_file0 = "/tmp/sim_atadev0"`	`dev_file0 = "/tmp/sim_atadev0"`
Line 900...	Line 891...

`dev_type1 = 0`	`dev_type1 = 0`
`dev_file1 = ""`	`dev_file1 = ""`
`dev_size1 = 0`	`dev_size1 = 0`
`dev_packet1 = 0`	`dev_packet1 = 0`
`enddevice`
`end`	`end`


	`/* CUC SECTION`

	`This section configures the OpenRISC Custom Unit Compiler`

	`memory_order = none/weak/strong/exact`
	`none different memory ordering, even if there are dependencies,`
	`burst can be made, width can change`
	`weak different memory ordering, if there cannot be dependencies`
	`burst can be made, width can change`
	`strong same memory ordering, burst can be made, width can change`
	`exact exacltly the same memory ordering and widths`

	`calling_convention = 0/1`
	`whether programs follow OpenRISC calling conventions`

	`enable_bursts = 0/1`
	`whether burst are detected`

	`no_multicycle = 0/1`
	`if selected no multicycle logic paths will be generated`

	`timings_fn = ""`
	`*/`

	`section cuc`
	`memory_order = weak`
	`calling_convention = 1`
	`enable_bursts = 1`
	`no_multicycle = 1`
	`timings_fn = "virtex.tim"`
	`end`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orpmon/] [sim.cfg] - Diff between revs 987 and 1495