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/* sim.cfg -- Simulator configuration script file
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/* sim.cfg -- Simulator configuration script file
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Copyright (C) 2001, Marko Mlinar, markom@opencores.org
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Copyright (C) 2001, Marko Mlinar, markom@opencores.org
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This file includes a lot of help about configurations and default one
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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It contains the default configuration and help about configuring
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the simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* INTRODUCTION
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/* INTRODUCTION
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The or1ksim have various parameters, which can be set in configuration
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The ork1sim has various parameters, that are set in configuration files
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files. Multiple configurations may be used and switched between at
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like this one. The user can switch between configurations at startup by
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or1ksim startup.
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specifying the required configuration file with the -f option.
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By default, or1ksim loads condfiguration file from './sim.cfg' and if not
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If no configuration file is specified or1ksim searches for the default
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found it checks '~/.or1k/sim.cfg'. If even this file is not found or
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configuration file sim.cfg. First it searches for './sim.cfg'. If this
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all parameters are not defined, default configuration is used.
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file is not found, it searches for '~/or1k/sim.cfg'. If this file is
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Users should not rely on default configuration, but rather redefine all
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not found too, it reverts to the built-in default configuration.
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critical settings, since default configuration may differ in newer
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versions of the or1ksim.
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NOTE: Users should not rely on the built-in configuration, since the
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If multiple configurations are used, user can switch between them by
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default configuration may differ between version.
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supplying -f option when starting simulator.
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Rather create a configuration file that sets all critical values.
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This file may contain (standard C) comments only - no // support.
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This file may contain (standard C) only comments - no // support.
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Configure files may be be included, using:
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include "file_name_to_include"
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Like normal configuration file, this file is divided in sections,
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Like normal configuration files, the included file is divided into
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where each section is described in detail also.
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sections. Each section is described in detail also.
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Some section also have subsections. One example of such subsection is
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Some section have subsections. One example of such a subsection is:
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block:
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device
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device
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instance specific parameters...
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instance specific parameters...
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enddevice
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enddevice
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Line 52... |
*/
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*/
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/* MEMORY SECTION
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/* MEMORY SECTION
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This section specifies how is initial memory generated and which blocks
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This section specifies how the memory is generated and the blocks
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it consist of.
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it consists of.
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type = random/unknown/pattern
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type = random/unknown/pattern
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specifies the initial memory values. 'random' parameter generate
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Specifies the initial memory values.
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random memory using seed 'random_seed' parameter. 'pattern' parameter
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'random' generates random memory using seed 'random_seed'.
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fills memory with 'pattern' parameter and 'unknown' does not specify
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'pattern' fills memory with 'pattern'.
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how memory should be generated - the fastest option.
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'unknown' does not specify how memory should be generated,
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leaving the memory in a undefined state. This is the fastest
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option.
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random_seed =
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random_seed =
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random seed for randomizer, used if type = random
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random seed for randomizer, used if type = 'random'.
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pattern =
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pattern =
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pattern to fill memory, used if type = pattern
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pattern to fill memory, used if type = 'pattern'.
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nmemories =
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nmemories =
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number of memory instances connected
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number of memory instances connected
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instance specific:
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instance specific:
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Line 91... |
cycles, required for read access, -1 if instance does not support reading
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cycles, required for read access, -1 if instance does not support reading
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delayw =
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delayw =
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cycles, required for write access, -1 if instance does not support writing
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cycles, required for write access, -1 if instance does not support writing
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16550 = 0/1
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0, if this device is uart 16450 and 1, if it is 16550
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log = ""
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log = ""
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filename, where to log memory accesses to, no log, if log command is not specified
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filename, where to log memory accesses to, no log, if log command is not specified
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*/
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*/
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section memory
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section memory
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/*random_seed = 12345
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/*random_seed = 12345
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type = random*/
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type = random*/
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pattern = 0x00
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pattern = 0x00
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type = unknown /* Fastest */
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type = unknown /* Fastest */
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nmemories = 3
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nmemories = 3
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device 0
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device 0
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name = "FLASH"
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name = "FLASH"
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ce = 0
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ce = 0
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baseaddr = 0x04000000
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baseaddr = 0x04000000
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size = 0x00800000
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size = 0x00800000
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delayr = 10
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delayr = 10
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delayw = -1
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delayw = -1
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/* log = "flash.log"*/
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enddevice
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enddevice
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device 1
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device 1
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name = "RAM"
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name = "RAM"
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ce = 1
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ce = 1
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baseaddr = 0x00000000
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baseaddr = 0x00000000
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size = 0x00400000
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size = 0x00400000
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delayr = 1
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delayr = 1
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delayw = 2
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delayw = 2
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/* log = "ram.log"*/
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enddevice
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enddevice
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device 2
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device 2
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name = "SRAM"
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name = "SRAM"
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ce = 2
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ce = 2
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baseaddr = 0x08000000
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baseaddr = 0x08000000
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size = 0x00400000
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size = 0x00400000
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delayr = 1
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delayr = 1
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delayw = 2
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delayw = 2
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/* log = "ram.log"*/
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enddevice
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enddevice
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end
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end
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/* IMMU SECTION
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/* IMMU SECTION
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This section configures Instruction Memory Menangement Unit
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This section configures the Instruction Memory Manangement Unit
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enabled = 0/1
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enabled = 0/1
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whether IMMU is enabled
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'0': disabled
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'1': enabled
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(NOTE: UPR bit is set)
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(NOTE: UPR bit is set)
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nsets =
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nsets =
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number of ITLB sets; must be power of two
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number of ITLB sets; must be power of two
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| Line 153... |
Line 156... |
entrysize =
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entrysize =
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instruction entry size in bytes
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instruction entry size in bytes
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ustates =
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ustates =
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number of ITLB usage states (2, 3, 4 etc., max is 4)
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number of ITLB usage states (2, 3, 4 etc., max is 4)
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hitdelay =
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number of cycles immu hit costs
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missdelay =
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number of cycles immu miss costs
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*/
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*/
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section immu
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section immu
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enabled = 1
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enabled = 1
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nsets = 64
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nsets = 64
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nways = 1
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nways = 1
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pagesize = 8192
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pagesize = 8192
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hitdelay = 0
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missdelay = 0
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end
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end
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/* DMMU SECTION
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/* DMMU SECTION
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This section configures Data Memory Menangement Unit
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This section configures the Data Memory Manangement Unit
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enabled = 0/1
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enabled = 0/1
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whether DMMU is enabled
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'0': disabled
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'1': enabled
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(NOTE: UPR bit is set)
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(NOTE: UPR bit is set)
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nsets =
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nsets =
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number of DTLB sets; must be power of two
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number of DTLB sets; must be power of two
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Line 197... |
entrysize =
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entrysize =
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data entry size in bytes
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data entry size in bytes
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ustates =
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ustates =
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number of DTLB usage states (2, 3, 4 etc., max is 4)
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number of DTLB usage states (2, 3, 4 etc., max is 4)
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hitdelay =
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number of cycles dmmu hit costs
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missdelay =
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number of cycles dmmu miss costs
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*/
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*/
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section dmmu
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section dmmu
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enabled = 1
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enabled = 1
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nsets = 64
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nsets = 64
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nways = 1
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nways = 1
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pagesize = 8192
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pagesize = 8192
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hitdelay = 0
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missdelay = 0
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end
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end
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/* IC SECTION
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/* IC SECTION
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This section configures Instruction Cache
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This section configures the Instruction Cache
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enabled = 0/1
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enabled = 0/1
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whether IC is enabled
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'0': disabled
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'1': enabled
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(NOTE: UPR bit is set)
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(NOTE: UPR bit is set)
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nsets =
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nsets =
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number of IC sets; must be power of two
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number of IC sets; must be power of two
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| Line 213... |
Line 235... |
blocksize =
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blocksize =
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IC block size in bytes; must be power of two
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IC block size in bytes; must be power of two
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ustates =
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ustates =
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number of IC usage states (2, 3, 4 etc., max is 4)
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number of IC usage states (2, 3, 4 etc., max is 4)
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hitdelay =
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number of cycles ic hit costs
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missdelay =
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number of cycles ic miss costs
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*/
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*/
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section ic
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section ic
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enabled = 1
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enabled = 1
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nsets = 256
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nsets = 256
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nways = 1
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nways = 1
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blocksize = 16
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blocksize = 16
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hitdelay = 0
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missdelay = 0
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end
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end
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/* DC SECTION
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/* DC SECTION
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This section configures Data Cache
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This section configures the Data Cache
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enabled = 0/1
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enabled = 0/1
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whether DC is enabled
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'0': disabled
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'1': enabled
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(NOTE: UPR bit is set)
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(NOTE: UPR bit is set)
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nsets =
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nsets =
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number of DC sets; must be power of two
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number of DC sets; must be power of two
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| Line 241... |
Line 273... |
blocksize =
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blocksize =
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DC block size in bytes; must be power of two
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DC block size in bytes; must be power of two
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ustates =
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ustates =
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number of DC usage states (2, 3, 4 etc., max is 4)
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number of DC usage states (2, 3, 4 etc., max is 4)
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load_hitdelay =
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number of cycles dc load hit costs
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load_missdelay =
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number of cycles dc load miss costs
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store_hitdelay =
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number of cycles dc load hit costs
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store_missdelay =
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number of cycles dc load miss costs
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*/
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*/
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section dc
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section dc
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enabled = 1
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enabled = 1
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nsets = 256
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nsets = 256
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nways = 1
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nways = 1
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blocksize = 16
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blocksize = 16
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load_hitdelay = 0
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load_missdelay = 0
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store_hitdelay = 0
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store_missdelay = 0
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end
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end
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/* SIM SECTION
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/* SIM SECTION
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This section specifies how should sim behave.
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This section specifies how or1ksim should behave.
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verbose = 0/1
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verbose = 0/1
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whether to print out extra messages
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'0': don't print extra messages
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'1': print extra messages
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debug = 0-9
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debug = 0-9
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= 0 disabled debug messages
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0 : no debug messages
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1-9 level of sim debug information, greater the number more verbose is
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1-9: debug message level.
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the output
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higher numbers produce more messages
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profile = 0/1
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profile = 0/1
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whether to generate profiling file 'sim.profile'
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'0': don't generate profiling file 'sim.profile'
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'1': don't generate profiling file 'sim.profile'
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prof_fn = ""
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prof_fn = ""
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filename, where to generate profiling info, used
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optional filename for the profiling file.
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only if 'profile' is set
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valid only if 'profile' is set
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mprofile = 0/1
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'0': don't generate memory profiling file 'sim.mprofile'
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'1': generate memory profiling file 'sim.mprofile'
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mprof_fn = ""
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optional filename for the memory profiling file.
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valid only if 'mprofile' is set
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history = 0/1
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history = 0/1
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whether instruction execution flow is tracked for
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'0': don't track execution flow
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display by simulator hist command. Useful for
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'1': track execution flow
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back-trace debugging.
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Execution flow can be tracked for the simulator's
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'hist' command. Useful for back-trace debugging.
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iprompt = 0/1
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iprompt = 0/1
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whether we strart in interactive prompt
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'0': start in (so what do we start in ???)
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'1': start in interactive prompt.
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exe_log = 0/1
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exe_log = 0/1
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whether execution log should be generated
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'0': don't generate execution log.
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'1': generate execution log.
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exe_log = default/hardware/simple/software
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type of execution log, default is used when not specified
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exe_log_start =
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index of first instruction to start logging, default = 0
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exe_log_end =
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index of last instruction to end logging; not limited, if omitted
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exe_log_marker =
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specifies number of instructions before horizontal marker is
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printed; if zero, markers are disabled (default)
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exe_log_fn = ""
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exe_log_fn = ""
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where to put execution log in, used only if 'exe_log'
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filename for the exection log file.
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is set
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valid only if 'exe_log' is set
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spr_log = 0/1
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'0': log reads/writes to/from sprs
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'1': don't log reads/write to/from sprs
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spr_log_fn = ""
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filename for the sprs log file.
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valid only if 'spr_log' is set
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clkcycle = [ps|ns|us|ms]
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clkcycle = [ps|ns|us|ms]
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specifies time measurement for one cycle
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specifies time measurement for one cycle
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*/
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*/
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| Line 294... |
Line 377... |
verbose = 0
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verbose = 0
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debug = 0
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debug = 0
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profile = 0
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profile = 0
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prof_fn = "sim.profile"
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prof_fn = "sim.profile"
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history = 0
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history = 1
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/* iprompt = 0 */
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/* iprompt = 0 */
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exe_log = 0
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exe_log = 0
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exe_log_type = software
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exe_log_type = software
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exe_log_start = 0
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exe_log_start = 0
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/* exe_log_end = 20000000*/
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/* exe_log_end = 20000000*/
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exe_log_marker = 10000
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exe_log_marker = 10000
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exe_log_fn = "executed.log"
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exe_log_fn = "executed.log"
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spr_log = 0
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spr_log_fn = "spr.log"
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clkcycle = 100ns
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end
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end
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/* SECTION VAPI
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/* SECTION VAPI
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This section configures Verification API, used for Advanced
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This section configures the Verification API, used for Advanced
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Core Verification.
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Core Verification.
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enabled = 0/1
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enabled = 0/1
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whether to start VAPI server
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'0': disbable VAPI server
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'1': enable/start VAPI server
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server_port =
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server_port =
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TCP/IP port to start VAPI server on
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TCP/IP port to start VAPI server on
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log_enabled = 0/1
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log_enabled = 0/1
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whether logging of VAPI requests is enabled
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'0': disable VAPI requests logging
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'1': enable VAPI requests logging
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hide_device_id = 0/1
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'0': don't log device id (for compatability with old version)
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'1': log device id
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vapi_fn =
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vapi_fn =
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specifies filename where to log into, if log_enabled is selected
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filename for the log file.
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valid only if log_enabled is set
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*/
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*/
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section VAPI
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section VAPI
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enabled = 0
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enabled = 0
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server_port = 9998
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server_port = 9998
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| Line 342... |
Line 437... |
specifies version and revision of the CPU used
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specifies version and revision of the CPU used
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upr =
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upr =
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changes the upr register
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changes the upr register
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sr =
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sets the initial Supervision Register value
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superscalar = 0/1
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superscalar = 0/1
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whether CPU is scalar or superscalar
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'0': CPU is scalar
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'1': CPU is superscalar
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(modify cpu/or32/execute.c to tune superscalar model)
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(modify cpu/or32/execute.c to tune superscalar model)
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hazards = 0/1
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hazards = 0/1
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whether data hazards are tracked in superscalar CPU
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'0': don't track data hazards in superscalar CPU
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and displayed by the simulator r command
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'1': track data hazards in superscalar CPU
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If tracked, data hazards can be displayed using the
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simulator's 'r' command.
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dependstats = 0/1
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dependstats = 0/1
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whether inter-instruction dependencies are calculated
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'0': don't calculate inter-instruction dependencies.
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and displayed by simulator stats command.
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'1': calculate inter-instruction dependencies.
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If calculated, inter-instruction dependencies can be
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displayed using the simulator's 'stat' command.
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slp = 0/1
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raw_range =
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calculation of subroutine level parallelism. Displayed
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range in cycles for raw register over time analysis, 0 = disabled
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by simulator stats command.
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btic = 0/1
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enable branch target instruction cache model
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bpb = 0/1
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sbuf_len =
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enable branch prediction buffer model
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length of store buffer (<= 256), 0 = disabled
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parameters for CPU analysis
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*/
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*/
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section cpu
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section cpu
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ver = 0x1200
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ver = 0x1200
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rev = 0x0001
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rev = 0x0001
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/* upr = */
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/* upr = */
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superscalar = 0
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superscalar = 0
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hazards = 0
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hazards = 0
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dependstats = 0
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dependstats = 0
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slp = 0
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end
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/* PM SECTION
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|
|
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This section specifies Power Management parameters
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|
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enabled = 0/1
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'0': disable power management
|
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'1': enable power management
|
|
*/
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|
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section pm
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enabled = 0
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end
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/* BPB SECTION
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|
|
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This section specifies how branch prediction should behave.
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|
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enabled = 0/1
|
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'0': disable branch prediction
|
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'1': enable branch prediction
|
|
|
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btic = 0/1
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'0': disable branch target instruction cache model
|
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'1': enable branch target instruction cache model
|
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|
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sbp_bf_fwd = 0/1
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Static branch prediction for 'l.bf'
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'0': don't use forward prediction
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'1': use forward prediction
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|
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sbp_bnf_fwd = 0/1
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Static branch prediction for 'l.bnf'
|
|
'0': don't use forward prediction
|
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'1': use forward prediction
|
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|
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hitdelay =
|
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number of cycles bpb hit costs
|
|
|
|
missdelay =
|
|
number of cycles bpb miss costs
|
|
*/
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|
|
|
section bpb
|
|
enabled = 0
|
btic = 0
|
btic = 0
|
bpb = 0
|
sbp_bf_fwd = 0
|
|
sbp_bnf_fwd = 0
|
|
hitdelay = 0
|
|
missdelay = 0
|
end
|
end
|
|
|
|
|
/* DEBUG SECTION
|
/* DEBUG SECTION
|
|
|
This sections specifies how debug unit should behave.
|
This sections specifies how the debug unit should behave.
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether debug unit is enabled
|
'0': disable debug unit
|
|
'1': enable debug unit
|
|
|
gdb_enabled = 0/1
|
gdb_enabled = 0/1
|
whether to start gdb server at 'server_port' port
|
'0': don't start gdb server
|
|
'1': start gdb server at port 'server_port'
|
|
|
server_port =
|
server_port =
|
TCP/IP port to start gdb server on, used only if gdb_enabled
|
TCP/IP port to start gdb server on
|
is set
|
valid only if gdb_enabled is set
|
|
|
|
vapi_id =
|
|
Used to create "fake" vapi log file containing the JTAG proxy messages.
|
|
*/
|
|
|
section debug
|
section debug
|
enabled = 0
|
enabled = 0
|
gdb_enabled = 0
|
gdb_enabled = 0
|
server_port = 9999
|
server_port = 9999
|
| Line 406... |
Line 559... |
/* MC SECTION
|
/* MC SECTION
|
|
|
This section configures the memory controller
|
This section configures the memory controller
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether memory controller is enabled
|
'0': disable memory controller
|
|
'1': enable memory controller
|
|
|
baseaddr =
|
baseaddr =
|
address of first MC register
|
address of first MC register
|
|
|
POC =
|
POC =
|
| Line 424... |
Line 578... |
end
|
end
|
|
|
|
|
/* UART SECTION
|
/* UART SECTION
|
|
|
This section configures UARTs
|
This section configures the UARTs
|
|
|
enabled = 0/1
|
|
whether uarts are enabled
|
|
|
|
nuarts =
|
nuarts =
|
make specified number of instances, configure each
|
make specified number of instances, configure each
|
instance within device - enddevice construct.
|
instance within device - enddevice construct.
|
|
|
instance specific:
|
instance specific:
|
baseaddr =
|
baseaddr =
|
address of first UART register for this device
|
address of first UART register for this device
|
|
|
rx_file = ""
|
rxfile = ""
|
filename, where to read data from
|
filename, where to read data from
|
|
|
tx_file = ""
|
txfile = ""
|
filename, where to write data to
|
filename, where to write data to
|
|
|
irq =
|
irq =
|
irq number for this device
|
irq number for this device
|
|
|
16550 = 0/1
|
16550 = 0/1
|
0, if this device is uart 16450 and 1, if it is 16550
|
'0': this device is a UART16450
|
|
'1': this device is a UART16550
|
|
|
jitter =
|
jitter =
|
in msecs... time to block, -1 to disable it
|
in msecs... time to block, -1 to disable it
|
|
|
vapi_id =
|
vapi_id =
|
VAPI id of this instance
|
VAPI id of this instance
|
*/
|
*/
|
|
|
section uart
|
section uart
|
enabled = 1
|
|
nuarts = 1
|
nuarts = 1
|
|
|
device 0
|
device 0
|
baseaddr = 0x90000000
|
baseaddr = 0x90000000
|
irq = 19
|
irq = 19
|
rxfile = "uart0.rx"
|
rxfile = "/tmp/uart0.rx"
|
txfile = "uart0.tx"
|
txfile = "/tmp/uart0.tx"
|
jitter = -1 /* async behaviour */
|
jitter = -1 /* async behaviour */
|
16550 = 1
|
16550 = 1
|
enddevice
|
enddevice
|
end
|
end
|
|
|
|
|
/* DMA SECTION
|
/* DMA SECTION
|
|
|
This section configures DMAs
|
This section configures the DMAs
|
|
|
enabled = 0/1
|
|
whether DMAs are enabled
|
|
|
|
ndmas =
|
ndmas =
|
make specified number of instances, configure each
|
make specified number of instances, configure each
|
instance within device - enddevice construct.
|
instance within device - enddevice construct.
|
|
|
| Line 494... |
Line 642... |
vapi_id =
|
vapi_id =
|
VAPI id of this instance
|
VAPI id of this instance
|
*/
|
*/
|
|
|
section dma
|
section dma
|
enabled = 0
|
ndmas = 0
|
ndmas = 1
|
|
|
|
|
/*
|
device 0
|
device 0
|
baseaddr = 0xa0000000
|
baseaddr = 0xa0000000
|
irq = 4
|
irq = 4
|
enddevice
|
enddevice
|
|
*/
|
end
|
end
|
|
|
|
|
/* ETHERNET SECTION
|
/* ETHERNET SECTION
|
|
|
This section configures ethernets
|
This section configures the ETHERNETs
|
|
|
enabled = 0/1
|
|
whether ethernets are enabled
|
|
|
|
nethernets =
|
nethernets =
|
make specified number of instances, configure each
|
make specified number of instances, configure each
|
instance within device - enddevice construct.
|
instance within device - enddevice construct.
|
|
|
| Line 522... |
Line 668... |
address of first ethernet register for this device
|
address of first ethernet register for this device
|
|
|
dma =
|
dma =
|
which controller is this ethernet "connected" to
|
which controller is this ethernet "connected" to
|
|
|
|
irq =
|
|
ethernet mac IRQ level
|
|
|
|
rtx_type =
|
|
use 0 - file interface, 1 - socket interface
|
|
|
rx_channel =
|
rx_channel =
|
DMA channel used for RX
|
DMA channel used for RX
|
|
|
tx_channel =
|
tx_channel =
|
DMA channel used for TX
|
DMA channel used for TX
|
|
|
rx_file = ""
|
rxfile = ""
|
filename, where to read data from
|
filename, where to read data from
|
|
|
tx_file = ""
|
txfile = ""
|
filename, where to write data to
|
filename, where to write data to
|
|
|
|
sockif = ""
|
|
interface name of ethernet socket
|
|
|
vapi_id =
|
vapi_id =
|
VAPI id of this instance
|
VAPI id of this instance
|
*/
|
*/
|
|
|
section ethernet
|
section ethernet
|
| Line 554... |
Line 709... |
txfile = "eth0.tx"
|
txfile = "eth0.tx"
|
sockif = "eth0"
|
sockif = "eth0"
|
enddevice
|
enddevice
|
end
|
end
|
|
|
|
|
|
/* GPIO SECTION
|
|
|
|
This section configures the GPIOs
|
|
|
|
ngpios =
|
|
make specified number of instances, configure each
|
|
instance within device - enddevice construct.
|
|
|
|
instance specific:
|
|
baseaddr =
|
|
address of first GPIO register for this device
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
base_vapi_id =
|
|
first VAPI id of this instance
|
|
GPIO uses 8 consecutive VAPI IDs
|
|
*/
|
|
|
|
section gpio
|
|
ngpios = 1
|
|
|
|
device 0
|
|
baseaddr = 0xA1000000
|
|
irq = 23
|
|
base_vapi_id = 0x0200
|
|
enddevice
|
|
end
|
|
|
|
/* VGA SECTION
|
|
|
|
This section configures the VGA/LCD controller
|
|
|
|
nvgas =
|
|
number of VGA devices connected
|
|
|
|
instance specific:
|
|
baseaddr =
|
|
address of first VGA register
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
refresh_rate =
|
|
number of cycles between screen dumps
|
|
|
|
filename = ""
|
|
template name for generated names (e.g. "primary" produces "primary0023.bmp")
|
|
*/
|
|
|
|
section vga
|
|
nvgas = 1
|
|
|
|
device 0
|
|
baseaddr = 0xb0000000
|
|
irq = 20
|
|
refresh_rate = 100000
|
|
filename = "primary"
|
|
enddevice
|
|
end
|
|
|
|
|
/* TICK TIMER SECTION
|
/* TICK TIMER SECTION
|
|
|
This section configures tick timer
|
This section configures tick timer
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether tick timer is enabled
|
whether tick timer is enabled
|
|
|
irq =
|
irq =
|
irq number
|
irq number
|
*/
|
*/
|
|
/*
|
section tick
|
section tick
|
enabled = 1
|
enabled = 1
|
irq = 0
|
irq = 0
|
end
|
end
|
|
*/
|
|
|
|
/* FB SECTION
|
|
|
|
This section configures the frame buffer
|
|
|
|
enabled = 0/1
|
|
whether frame buffer is enabled
|
|
|
|
baseaddr =
|
|
base address of frame buffer
|
|
|
|
paladdr =
|
|
base address of first palette entry
|
|
|
|
refresh_rate =
|
|
number of cycles between screen dumps
|
|
|
|
filename = ""
|
|
template name for generated names (e.g. "primary" produces "primary0023.bmp")
|
|
*/
|
|
|
section fb
|
section fb
|
enabled = 1
|
enabled = 1
|
baseaddr = 0xc0000000
|
baseaddr = 0xc0000000
|
refresh_rate = 1000000
|
refresh_rate = 1000000
|
filename = "primary"
|
filename = "primary"
|
end
|
end
|
|
|
|
|
/* KBD SECTION
|
/* KBD SECTION
|
|
|
This section configures PS/2 compatible keyboard
|
This section configures the PS/2 compatible keyboard
|
|
|
enabled = 0/1
|
enabled = 0/1
|
whether keyboard is enabled
|
whether keyboard is enabled
|
|
|
baseaddr =
|
baseaddr =
|
| Line 598... |
Line 839... |
irq = 12
|
irq = 12
|
baseaddr = 0x98000000
|
baseaddr = 0x98000000
|
rxfile = "kbd.rx"
|
rxfile = "kbd.rx"
|
end
|
end
|
|
|
|
|
|
/* ATA SECTION
|
|
|
|
This section configures the ATA/ATAPI host controller
|
|
|
|
natas =
|
|
number of ATA hosts connected
|
|
|
|
instance specific:
|
|
baseaddr =
|
|
address of first ATA register
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
debug =
|
|
debug level for ata models.
|
|
0: no debug messages
|
|
1: verbose messages
|
|
3: normal messages (more messages than verbose)
|
|
5: debug messages (normal debug messages)
|
|
7: flow control messages (debug statemachine flows)
|
|
9: low priority message (display everything the code does)
|
|
|
|
dev_type0/1 =
|
|
ata device 0 type
|
|
0: NO_CONNeCT: none (not connected)
|
|
1: FILE : simulated harddisk
|
|
2: LOCAL : local system harddisk
|
|
|
|
dev_file0/1 = ""
|
|
filename for simulated ATA device
|
|
valid only if dev_type0 == 1
|
|
|
|
dev_size0/1 =
|
|
size of simulated hard-disk (in MBytes)
|
|
valid only if dev_type0 == 1
|
|
|
|
dev_packet0/1 =
|
|
0: simulated ATA device does NOT implement PACKET command feature set
|
|
1: simulated ATA device does implement PACKET command feature set
|
|
|
|
FIXME: irq number
|
|
*/
|
|
|
|
section ata
|
|
natas = 1
|
|
|
|
device 0
|
|
baseaddr = 0xc8000000
|
|
irq = 21
|
|
|
|
dev_type0 = 1
|
|
dev_file0 = "/tmp/sim_atadev0"
|
|
dev_size0 = 1
|
|
dev_packet0 = 0
|
|
|
|
dev_type1 = 0
|
|
dev_file1 = ""
|
|
dev_size1 = 0
|
|
dev_packet1 = 0
|
|
enddevice
|
|
end
|
