URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 1327 and 1581

Rev 1327	Rev 1581
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1.1.1 2004/12/13 17:15:47 jcastillo`
	`// Firt import of OR1200 over Celoxica RC203 platform`
	`//`
`// Revision 1.42 2004/06/08 18:17:36 lampret`	`// Revision 1.42 2004/06/08 18:17:36 lampret`
`// Non-functional changes. Coding style fixes.`	`// Non-functional changes. Coding style fixes.`
`//`	`//`
`// Revision 1.41 2004/05/09 20:03:20 lampret`	`// Revision 1.41 2004/05/09 20:03:20 lampret`
`// By default l.cust5 insns are disabled`	`// By default l.cust5 insns are disabled`
Line 313...	Line 316...

`//`	`//`
`// Target FPGA memories`	`// Target FPGA memories`
`//`	`//`
//`define OR1200_ALTERA_LPM	//`define OR1200_ALTERA_LPM
`define OR1200_XILINX_RAMB	`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D	//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D	//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
`//`	`//`
`// Do not implement Data cache`	`// Do not implement Data cache`
`//`	`//`