OpenCores

Rev 666	Rev 681
Line 10...	Line 10...
`#define UART_BASE_ADD 0x9c000000`	`#define UART_BASE_ADD 0x9c000000`
`#define MC_BASE_ADD 0xa0000000`	`#define MC_BASE_ADD 0xa0000000`
`#define CRT_BASE_ADD 0xb0000000`	`#define CRT_BASE_ADD 0xb0000000`

`/* Define this if you want to use I and/or D cache */`	`/* Define this if you want to use I and/or D cache */`
`#define ICACHE 1`	`#define ICACHE 0`
`#define DCACHE 1`	`#define DCACHE 0`

`#define IC_SIZE 4096`	`#define IC_SIZE 4096`
`#define IC_LINE 16`	`#define IC_LINE 16`
`#define DC_SIZE 4096`	`#define DC_SIZE 4096`
`#define DC_LINE 16`	`#define DC_LINE 16`

`/* Define this if you want to use I and/or D MMU */`	`/* Define this if you want to use I and/or D MMU */`
`#define IMMU 0`	`#define IMMU 0`
`#define DMMU 1`	`#define DMMU 0`

`#define DMMU_SET_NB 64`	`#define DMMU_SET_NB 64`
`#define DMMU_PAGE_ADD_BITS 13 /* 13 for 8k, 12 for 4k page size */`	`#define DMMU_PAGE_ADD_BITS 13 /* 13 for 8k, 12 for 4k page size */`
`#define DMMU_PAGE_ADD_MASK 0x3fff /* 0x3fff for 8k, 0x1fff for 4k page size */`	`#define DMMU_PAGE_ADD_MASK 0x3fff /* 0x3fff for 8k, 0x1fff for 4k page size */`
`#define DMMU_SET_ADD_MASK 0x3f /* 0x3f for, 64 0x7f for 128 nuber of sets */`	`#define DMMU_SET_ADD_MASK 0x3f /* 0x3f for, 64 0x7f for 128 nuber of sets */`

Line 10...

#define UART_BASE_ADD   0x9c000000

#define UART_BASE_ADD   0x9c000000

#define MC_BASE_ADD     0xa0000000

#define MC_BASE_ADD     0xa0000000

#define CRT_BASE_ADD    0xb0000000

#define CRT_BASE_ADD    0xb0000000

/* Define this if you want to use I and/or D cache */

/* Define this if you want to use I and/or D cache */

#define ICACHE          1

#define ICACHE          0

#define DCACHE          1

#define DCACHE          0

#define IC_SIZE         4096

#define IC_SIZE         4096

#define IC_LINE         16

#define IC_LINE         16

#define DC_SIZE         4096

#define DC_SIZE         4096

#define DC_LINE         16

#define DC_LINE         16

/* Define this if you want to use I and/or D MMU */

/* Define this if you want to use I and/or D MMU */

#define IMMU                        0

#define IMMU                        0

#define DMMU                        1

#define DMMU                        0

#define DMMU_SET_NB                 64

#define DMMU_SET_NB                 64

#define DMMU_PAGE_ADD_BITS          13      /* 13 for 8k, 12 for 4k page size */

#define DMMU_PAGE_ADD_BITS          13      /* 13 for 8k, 12 for 4k page size */

#define DMMU_PAGE_ADD_MASK          0x3fff  /* 0x3fff for 8k, 0x1fff for 4k page size */

#define DMMU_PAGE_ADD_MASK          0x3fff  /* 0x3fff for 8k, 0x1fff for 4k page size */

#define DMMU_SET_ADD_MASK           0x3f    /* 0x3f for, 64 0x7f for 128 nuber of sets */

#define DMMU_SET_ADD_MASK           0x3f    /* 0x3f for, 64 0x7f for 128 nuber of sets */

Browse