| Line 5... |
Line 5... |
/* System clock frequecy */
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/* System clock frequecy */
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#define SYS_CLK 25000000
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#define SYS_CLK 25000000
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/* Memory organization */
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/* Memory organization */
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#define SRAM_BASE_ADD 0x00000000
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#define SRAM_BASE_ADD 0x00000000
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#define FLASH_BASE_ADD 0x04000000
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#define FLASH_BASE_ADD 0xf0000000
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/* Devices base address */
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/* Devices base address */
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#define UART_BASE_ADD 0x90000000
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#define UART_BASE_ADD 0x90000000
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#define MC_BASE_ADD 0x60000000
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#define MC_BASE_ADD 0x93000000
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#define CRT_BASE_ADD 0xc0000000
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#define CRT_BASE_ADD 0x97000000
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#define FBMEM_BASE_ADD 0xa8000000
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#define FBMEM_BASE_ADD 0xa8000000
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#define ETH_BASE_ADD 0xd0000000
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#define ETH_BASE_ADD 0x92000000
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#define KBD_BASE_ADD 0x98000000
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#define KBD_BASE_ADD 0x94000000
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/* Define this if you want to use I and/or D cache */
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/* Define this if you want to use I and/or D cache */
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#define ICACHE 0
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#define ICACHE 0
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#define DCACHE 0
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#define DCACHE 0
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| Line 43... |
Line 43... |
/* Define this if you are using MC */
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/* Define this if you are using MC */
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#define MC_INIT 1
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#define MC_INIT 1
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/* Memory controller initialize values */
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/* Memory controller initialize values */
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#define MC_CSR_VAL 0x0B000300
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#define MC_CSR_VAL 0x0B000300
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#define MC_MASK_VAL 0x000000e0
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#define MC_MASK_VAL 0x000003f0
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#define FLASH_BASE_ADD 0x04000000
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#define FLASH_TMS_VAL 0x00000103
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#define FLASH_TMS_VAL 0x00102102
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#define SDRAM_BASE_ADD 0x00000000
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#define SDRAM_BASE_ADD 0x00000000
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#define SDRAM_TMS_VAL 0x07248230
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#define SDRAM_TMS_VAL 0x19220057
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/* Define ethernet MAC address */
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/* Define ethernet MAC address */
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#define MACADDR0 0x00
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#define MACADDR0 0x00
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#define MACADDR1 0x01
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#define MACADDR1 0x01
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#define MACADDR2 0x02
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#define MACADDR2 0x02
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