URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [sim.cfg] - Diff between revs 743 and 753

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 743	Rev 753
Line 100...	Line 100...
`/*random_seed = 12345`	`/*random_seed = 12345`
`type = random*/`	`type = random*/`
`pattern = 0x00`	`pattern = 0x00`
`type = unknown /* Fastest */`	`type = unknown /* Fastest */`

`nmemories = 2`	`nmemories = 3`
`device 0`	`device 0`
`name = "FLASH"`	`name = "FLASH"`
`ce = 0`	`ce = 0`
`baseaddr = 0x04000000`	`baseaddr = 0x04000000`
`size = 0x00400000`	`size = 0x00800000`
`delayr = 10`	`delayr = 10`
`delayw = -1`	`delayw = -1`
`/* log = "flash.log"*/`	`/* log = "flash.log"*/`
`enddevice`	`enddevice`

Line 120...	Line 120...
`size = 0x00800000`	`size = 0x00800000`
`delayr = 1`	`delayr = 1`
`delayw = 2`	`delayw = 2`
`/* log = "ram.log"*/`	`/* log = "ram.log"*/`
`enddevice`	`enddevice`
	`device 2`
	`name = "SRAM"`
	`ce = 2`
	`baseaddr = 0x08000000`
	`size = 0x00400000`
	`delayr = 1`
	`delayw = 2`
	`/* log = "ram.log"*/`
	`enddevice`
`end`	`end`

`/* IMMU SECTION`	`/* IMMU SECTION`

`This section configures Instruction Memory Menangement Unit`	`This section configures Instruction Memory Menangement Unit`
Line 408...	Line 417...
`Power On Configuration register`	`Power On Configuration register`
`*/`	`*/`

`section mc`	`section mc`
`enabled = 1`	`enabled = 1`
`baseaddr = 0xa0000000`	`baseaddr = 0x60000000`
`POC = 0x00000008 /* Power on configuration register */`	`POC = 0x00000008 /* Power on configuration register */`
`end`	`end`


`/* UART SECTION`	`/* UART SECTION`
Line 452...	Line 461...
`section uart`	`section uart`
`enabled = 1`	`enabled = 1`
`nuarts = 1`	`nuarts = 1`

`device 0`	`device 0`
`baseaddr = 0x9c000000`	`baseaddr = 0x90000000`
`irq = 15`	`irq = 19`
`rxfile = "uart0.rx"`	`rxfile = "uart0.rx"`
`txfile = "uart0.tx"`	`txfile = "uart0.tx"`
`jitter = -1 /* async behaviour */`	`jitter = -1 /* async behaviour */`
`16550 = 1`	`16550 = 1`
`enddevice`	`enddevice`
Line 489...	Line 498...
`section dma`	`section dma`
`enabled = 0`	`enabled = 0`
`ndmas = 1`	`ndmas = 1`

`device 0`	`device 0`
`baseaddr = 0x90000000`	`baseaddr = 0xa0000000`
`irq = 4`	`irq = 4`
`enddevice`	`enddevice`
`end`	`end`


Line 533...	Line 542...

`section ethernet`	`section ethernet`
`nethernets = 1`	`nethernets = 1`

`device 0`	`device 0`
`baseaddr = 0xb2000000`	`baseaddr = 0xd0000000`
`dma = 0`	`dma = 0`
`irq = 16`	`irq = 15`
`rtx_type = 1`	`rtx_type = 0`
`tx_channel = 0`	`tx_channel = 0`
`rx_channel = 1`	`rx_channel = 1`
`rxfile = "/tmp/eth0.rx"`	`rxfile = "eth0.rx"`
`txfile = "/tmp/eth0.tx"`	`txfile = "eth0.tx"`
`sockif = "eth0"`	`sockif = "eth0"`
`enddevice`	`enddevice`
`end`	`end`

`/* TICK TIMER SECTION`	`/* TICK TIMER SECTION`
Line 563...	Line 572...
`irq = 0`	`irq = 0`
`end`	`end`

`section fb`	`section fb`
`enabled = 1`	`enabled = 1`
`baseaddr = 0xb0000000`	`baseaddr = 0xc0000000`
`refresh_rate = 1000000`	`refresh_rate = 1000000`
`filename = "primary"`	`filename = "primary"`
`end`	`end`

`/* KBD SECTION`	`/* KBD SECTION`
Line 584...	Line 593...
`filename, where to read data from`	`filename, where to read data from`
`*/`	`*/`

`section kbd`	`section kbd`
`enabled = 1`	`enabled = 1`
`irq = 21`	`irq = 12`
`baseaddr = 0xb1000000`	`baseaddr = 0x98000000`
`rxfile = "kbd.rx"`	`rxfile = "kbd.rx"`
`end`	`end`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [sim.cfg] - Diff between revs 743 and 753