| Line 54... |
Line 54... |
oraddr_t tagaddr; /* tag address */
|
oraddr_t tagaddr; /* tag address */
|
int lru; /* least recently used */
|
int lru; /* least recently used */
|
} way[MAX_DC_WAYS];
|
} way[MAX_DC_WAYS];
|
} dc[MAX_DC_SETS];
|
} dc[MAX_DC_SETS];
|
|
|
void dc_info()
|
void dc_info(void)
|
{
|
{
|
if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP)) {
|
PRINTF("DCache not implemented. Set UPR[DCP].\n");
|
PRINTF("DCache not implemented. Set UPR[DCP].\n");
|
return;
|
return;
|
}
|
}
|
|
|
PRINTF("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
|
PRINTF("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
|
| Line 84... |
Line 84... |
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
oraddr_t tagaddr;
|
oraddr_t tagaddr;
|
uint32_t tmp;
|
uint32_t tmp;
|
|
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
|
(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
|
!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) ||
|
data_ci) {
|
data_ci) {
|
if (width == 4)
|
if (width == 4)
|
tmp = evalsim_mem32(dataaddr, virt_addr);
|
tmp = evalsim_mem32(dataaddr, virt_addr);
|
else if (width == 2)
|
else if (width == 2)
|
tmp = evalsim_mem16(dataaddr, virt_addr);
|
tmp = evalsim_mem16(dataaddr, virt_addr);
|
| Line 205... |
Line 205... |
else if (width == 2)
|
else if (width == 2)
|
setsim_mem16(dataaddr, virt_addr, data);
|
setsim_mem16(dataaddr, virt_addr, data);
|
else if (width == 1)
|
else if (width == 1)
|
setsim_mem8(dataaddr, virt_addr, data);
|
setsim_mem8(dataaddr, virt_addr, data);
|
|
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
|
(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
|
!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) ||
|
data_ci ||
|
data_ci || !cur_area)
|
(!cur_area))
|
|
return;
|
return;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
| Line 284... |
Line 283... |
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
oraddr_t tagaddr;
|
oraddr_t tagaddr;
|
|
|
if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
|
return;
|
return;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
|
|
if (!testsprbits(SPR_SR, SPR_SR_DCE)) {
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE)) {
|
for (i = 0; i < config.dc.nways; i++) {
|
for (i = 0; i < config.dc.nways; i++) {
|
dc[set].way[i].tagaddr = -1;
|
dc[set].way[i].tagaddr = -1;
|
dc[set].way[i].lru = 0;
|
dc[set].way[i].lru = 0;
|
}
|
}
|
return;
|
return;
|
| Line 314... |
Line 313... |
|
|
/*-----------------------------------------------------[ DC configuration ]---*/
|
/*-----------------------------------------------------[ DC configuration ]---*/
|
void dc_enabled(union param_val val, void *dat)
|
void dc_enabled(union param_val val, void *dat)
|
{
|
{
|
config.dc.enabled = val.int_val;
|
config.dc.enabled = val.int_val;
|
setsprbits (SPR_UPR, SPR_UPR_DCP, val.int_val ? 1 : 0);
|
if(val.int_val)
|
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DCP;
|
|
else
|
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DCP;
|
}
|
}
|
|
|
void dc_nsets(union param_val val, void *dat)
|
void dc_nsets(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val) && val.int_val <= MAX_DC_SETS){
|
if (is_power2(val.int_val) && val.int_val <= MAX_DC_SETS){
|
config.dc.nsets = val.int_val;
|
config.dc.nsets = val.int_val;
|
setsprbits (SPR_DCCFGR, SPR_DCCFGR_NCS, log2(val.int_val));
|
cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCS;
|
|
cpu_state.sprs[SPR_DCCFGR] |= log2(val.int_val) << 3;
|
}
|
}
|
else {
|
else {
|
char tmp[200];
|
char tmp[200];
|
sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_DC_SETS);
|
sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_DC_SETS);
|
CONFIG_ERROR(tmp);
|
CONFIG_ERROR(tmp);
|
| Line 334... |
Line 337... |
|
|
void dc_nways(union param_val val, void *dat)
|
void dc_nways(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val) && val.int_val <= MAX_DC_WAYS){
|
if (is_power2(val.int_val) && val.int_val <= MAX_DC_WAYS){
|
config.dc.nways = val.int_val;
|
config.dc.nways = val.int_val;
|
setsprbits (SPR_DCCFGR, SPR_DCCFGR_NCW, log2(val.int_val));
|
cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCW;
|
|
cpu_state.sprs[SPR_DCCFGR] |= log2(val.int_val);
|
}
|
}
|
else{
|
else{
|
char tmp[200];
|
char tmp[200];
|
sprintf (tmp, "value of power of two and lower or equal than %i expected.",
|
sprintf (tmp, "value of power of two and lower or equal than %i expected.",
|
MAX_DC_WAYS);
|
MAX_DC_WAYS);
|
| Line 348... |
Line 352... |
|
|
void dc_blocksize(union param_val val, void *dat)
|
void dc_blocksize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val)) {
|
if (is_power2(val.int_val)) {
|
config.dc.blocksize = val.int_val;
|
config.dc.blocksize = val.int_val;
|
setsprbits (SPR_DCCFGR, SPR_DCCFGR_CBS,log2(val.int_val));
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_CBS;
|
|
cpu_state.sprs[SPR_ICCFGR] |= log2(val.int_val) << 7;
|
} else
|
} else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void dc_ustates(union param_val val, void *dat)
|
void dc_ustates(union param_val val, void *dat)
|
