| Line 83... |
Line 83... |
uint32_t dc_simulate_read(oraddr_t dataaddr, oraddr_t virt_addr, int width)
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uint32_t dc_simulate_read(oraddr_t dataaddr, oraddr_t virt_addr, int width)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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uint32_t tmp;
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uint32_t tmp = 0;
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
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!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) ||
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!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) ||
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data_ci) {
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data_ci) {
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if (width == 4)
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if (width == 4)
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| Line 146... |
Line 146... |
minlru = dc[set].way[i].lru;
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minlru = dc[set].way[i].lru;
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}
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}
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}
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}
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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/* FIXME: What is the virtual address meant to be? (ie. What happens if
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/* FIXME: What is the virtual address meant to be? (ie. What happens if
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* we read out of memory while refilling a cache line?) */
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* we read out of memory while refilling a cache line?) */
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~ADDR_C(3)) + i) & (config.dc.blocksize - 1)), 0);
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tmp = evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~ADDR_C(3)) + i) & (config.dc.blocksize - 1)), 0);
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = tmp;
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if(!cur_area) {
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if(!cur_area) {
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].lru = 0;
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dc[set].way[minway].lru = 0;
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return 0;
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return 0;
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} else if (cur_area->log)
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} else if (cur_area->log)
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| Line 178... |
Line 179... |
else if (width == 1) {
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else if (width == 1) {
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tmp = (tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff;
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tmp = (tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff;
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return tmp;
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return tmp;
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}
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}
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}
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}
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return 0;
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC write hit stats,
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- increment DC write hit stats,
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- set 'lru' at this way to config.dc.ustates - 1 and
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- set 'lru' at this way to config.dc.ustates - 1 and
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