| Line 96... |
Line 96... |
/* If we're single stepping, always stop */
|
/* If we're single stepping, always stop */
|
if((action == DebugInstructionFetch) && (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST))
|
if((action == DebugInstructionFetch) && (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST))
|
return 1;
|
return 1;
|
|
|
/* is any watchpoint enabled to generate a break or count? If not, ignore */
|
/* is any watchpoint enabled to generate a break or count? If not, ignore */
|
if(mfspr(SPR_DMR2) & (SPR_DMR2_WGB | SPR_DMR2_AWTC))
|
if(cpu_state.sprs[SPR_DMR2] & (SPR_DMR2_WGB | SPR_DMR2_AWTC))
|
return calculate_watchpoints(action, udata);
|
return calculate_watchpoints(action, udata);
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
| Line 116... |
Line 116... |
int match = 0;
|
int match = 0;
|
int DCR_hit = 0;
|
int DCR_hit = 0;
|
|
|
/* Calculate first 8 matchpoints, result is put into DCR_hit */
|
/* Calculate first 8 matchpoints, result is put into DCR_hit */
|
if (i < 8) {
|
if (i < 8) {
|
unsigned long dcr = mfspr(SPR_DCR(i));
|
unsigned long dcr = cpu_state.sprs[SPR_DCR(i)];
|
unsigned long dcr_ct = dcr & SPR_DCR_CT; /* the CT field alone */
|
unsigned long dcr_ct = dcr & SPR_DCR_CT; /* the CT field alone */
|
/* Is this matchpoint a propos for the current action? */
|
/* Is this matchpoint a propos for the current action? */
|
if ( ((dcr & SPR_DCR_DP) && dcr_ct) && /* DVR/DCP pair present */
|
if ( ((dcr & SPR_DCR_DP) && dcr_ct) && /* DVR/DCP pair present */
|
(((action==DebugInstructionFetch) && (dcr_ct == SPR_DCR_CT_IFEA)) ||
|
(((action==DebugInstructionFetch) && (dcr_ct == SPR_DCR_CT_IFEA)) ||
|
((action==DebugLoadAddress) && ((dcr_ct == SPR_DCR_CT_LEA) ||
|
((action==DebugLoadAddress) && ((dcr_ct == SPR_DCR_CT_LEA) ||
|
| Line 130... |
Line 130... |
((action==DebugLoadData) && ((dcr_ct == SPR_DCR_CT_LD) ||
|
((action==DebugLoadData) && ((dcr_ct == SPR_DCR_CT_LD) ||
|
(dcr_ct == SPR_DCR_CT_LSD))) ||
|
(dcr_ct == SPR_DCR_CT_LSD))) ||
|
((action==DebugStoreData) && ((dcr_ct == SPR_DCR_CT_SD) ||
|
((action==DebugStoreData) && ((dcr_ct == SPR_DCR_CT_SD) ||
|
(dcr_ct == SPR_DCR_CT_LSD)))) ) {
|
(dcr_ct == SPR_DCR_CT_LSD)))) ) {
|
unsigned long op1 = udata;
|
unsigned long op1 = udata;
|
unsigned long op2 = mfspr (SPR_DVR(i));
|
unsigned long op2 = cpu_state.sprs[SPR_DVR(i)];
|
/* Perform signed comparison? */
|
/* Perform signed comparison? */
|
if (dcr & SPR_DCR_SC) {
|
if (dcr & SPR_DCR_SC) {
|
long sop1 = op1, sop2 = op2; /* Convert to signed */
|
long sop1 = op1, sop2 = op2; /* Convert to signed */
|
switch(dcr & SPR_DCR_CC) {
|
switch(dcr & SPR_DCR_CC) {
|
case SPR_DCR_CC_MASKED: DCR_hit = sop1 & sop2; break;
|
case SPR_DCR_CC_MASKED: DCR_hit = sop1 & sop2; break;
|
| Line 427... |
Line 427... |
|
|
/* debug_ignore_exception returns 1 if the exception should be ignored. */
|
/* debug_ignore_exception returns 1 if the exception should be ignored. */
|
int debug_ignore_exception (unsigned long except)
|
int debug_ignore_exception (unsigned long except)
|
{
|
{
|
int result = 0;
|
int result = 0;
|
unsigned long dsr = mfspr (SPR_DSR);
|
unsigned long dsr = cpu_state.sprs[SPR_DSR];
|
unsigned long drr = mfspr (SPR_DRR);
|
unsigned long drr = cpu_state.sprs[SPR_DRR];
|
|
|
#if DEBUG_JTAG
|
#if DEBUG_JTAG
|
PRINTF ("dsr 0x%08x drr 0x%08x \n", dsr, drr);
|
PRINTF ("dsr 0x%08x drr 0x%08x \n", dsr, drr);
|
#endif
|
#endif
|
|
|
| Line 455... |
Line 455... |
}
|
}
|
#if DEBUG_JTAG
|
#if DEBUG_JTAG
|
PRINTF ("dsr 0x%08x drr 0x%08x result %i\n", dsr, drr, result);
|
PRINTF ("dsr 0x%08x drr 0x%08x result %i\n", dsr, drr, result);
|
#endif
|
#endif
|
|
|
mtspr (SPR_DRR, drr);
|
cpu_state.sprs[SPR_DRR] = drr;
|
set_stall_state (result != 0);
|
set_stall_state (result != 0);
|
return (result != 0);
|
return (result != 0);
|
}
|
}
|
|
|
/*--------------------------------------------------[ Debug configuration ]---*/
|
/*--------------------------------------------------[ Debug configuration ]---*/
|
