| Line 62... |
Line 62... |
if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
|
if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
|
TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
|
TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
|
except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
|
except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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} else if(cpu_state.sprs[SPR_PICSR] & (1 << (int)dat))
|
} else if(cpu_state.sprs[SPR_PICSR] & (1 << (int)dat))
|
/* Reschedule only if the interrupt hasn't been cleared */
|
/* Reschedule only if the interrupt hasn't been cleared */
|
SCHED_ADD(pic_clock, dat, 1);
|
sched_next_insn(pic_clock, dat);
|
}
|
}
|
|
|
/* WARNING: Don't eaven try and call this function *during* a simulated
|
/* WARNING: Don't eaven try and call this function *during* a simulated
|
* instruction!! (as in during a read_mem or write_mem callback). except_handle
|
* instruction!! (as in during a read_mem or write_mem callback). except_handle
|
* assumes that this is the case, it breaks otherwise. */
|
* assumes that this is the case, it breaks otherwise. */
|
| Line 87... |
Line 87... |
if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
|
TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
|
TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
|
except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
|
except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
|
} else
|
} else
|
/* Interrupts not currently enabled, retry next clock cycle */
|
/* Interrupts not currently enabled, retry next clock cycle */
|
SCHED_ADD(pic_clock, (void *)line, 1);
|
sched_next_insn(pic_clock, (void *)line);
|
}
|
}
|
}
|
}
|
|
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No newline at end of file
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No newline at end of file
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