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[/] [or1k_old/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [testbench/] [acv_uart.c] - Diff between revs 1497 and 1498

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Rev 1497 Rev 1498
Line 510... Line 510...
  printf ("interrupt_test\n");
  printf ("interrupt_test\n");
  /* Configure UART for interrupt mode */
  /* Configure UART for interrupt mode */
  ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
  ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
  setreg (UART_LCR, LCR_DIVL);
  setreg (UART_LCR, LCR_DIVL);
  setreg (UART_DLH, 12 >> 8);            /* Set relatively slow speed, so we can hanlde interrupts properly */
  setreg (UART_DLH, 12 >> 8);            /* Set relatively slow speed, so we can hanlde interrupts properly */
  setreg (UART_DLL, 12 & 0xff);
  setreg (UART_DLL, 6 & 0xff);
  setreg (UART_LCR, 0x03);    /* 8N1 @ 6 */
  setreg (UART_LCR, 0x03);    /* 8N1 @ 6 */
 
 
  ASSERT (int_cnt == 0);   /* We should not have got any interrupts before this test */
  ASSERT (int_cnt == 0);   /* We should not have got any interrupts before this test */
  setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
  setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
  setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
  setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
Line 721... Line 721...
  ASSERT (getreg (UART_LSR) == 0x60);  /* nothing happening */
  ASSERT (getreg (UART_LSR) == 0x60);  /* nothing happening */
  send_char ('!');
  send_char ('!');
  recv_char ('!');
  recv_char ('!');
  MARK ();
  MARK ();
 
 
 
  /* Make sure the TX fifo and the TX serial reg. are empty */
 
  ASSERT (getreg (UART_LSR) & LSR_TXFE);
 
  ASSERT (getreg (UART_LSR) & LSR_TXE);
 
 
  /* FCR2 - reset tx FIFO */
  /* FCR2 - reset tx FIFO */
send_char_no_wait ('1');
send_char_no_wait ('1');
send_char_no_wait ('2');
send_char_no_wait ('2');
//  send_char ('1');
//  send_char ('1');
//  send_char ('2');
//  send_char ('2');
  setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
  setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
  ASSERT (getreg (UART_LSR) == 0x00);  /* we should still be sending '1' */
  ASSERT (getreg (UART_LSR) == 0x20);  /* we should still be sending '1' */
  NO_ERROR();
  NO_ERROR();
  send_char ('*');
  send_char ('*');
  recv_char ('*');
  recv_char ('*');
  MARK ();
  MARK ();
 
 

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