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https://opencores.org/ocsvn/or1k_old/or1k_old/trunk
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| Rev 1424 |
Rev 1486 |
| Line 21... |
Line 21... |
/*random_seed = 12345
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/*random_seed = 12345
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type = random*/
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type = random*/
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pattern = 0x00
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pattern = 0x00
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type = unknown /* Fastest */
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type = unknown /* Fastest */
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nmemories = 2
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device 0
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name = "FLASH"
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name = "FLASH"
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ce = 0
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ce = 0
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mc = 0
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baseaddr = 0xf0000000
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baseaddr = 0xf0000000
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size = 0x00200000
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size = 0x00200000
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delayr = 10
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delayr = 10
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delayw = -1
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delayw = -1
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enddevice
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end
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section memory
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/*random_seed = 12345
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type = random*/
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pattern = 0x00
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type = unknown /* Fastest */
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device 1
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name = "RAM"
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name = "RAM"
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ce = 1
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ce = 1
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mc = 0
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baseaddr = 0x00000000
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baseaddr = 0x00000000
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size = 0x00200000
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size = 0x00200000
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delayr = 2
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delayr = 2
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delayw = 4
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delayw = 4
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enddevice
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end
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end
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section immu
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section immu
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enabled = 1
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enabled = 1
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nsets = 64
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nsets = 64
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