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#include "support.h"
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#include "support.h"
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/* Define RAM physical location and size
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/* Define RAM physical location and size
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Bottom half will be used for this program, the rest
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Bottom half will be used for this program, the rest
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will be used for testing */
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will be used for testing */
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#define FLASH_START 0x00000000
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#define FLASH_SIZE 0x00200000
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#define RAM_START 0x40000000
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#define RAM_START 0x40000000
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#define RAM_SIZE 0x00200000
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#define RAM_SIZE 0x00200000
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/* What is the last address in ram that is used by this program */
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/* What is the last address in ram that is used by this program */
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#define CODE_END_ADD (RAM_START + (RAM_SIZE / 2))
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#define TEXT_END_ADD (FLASH_START + (FLASH_SIZE / 2))
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#define DATA_END_ADD (RAM_START + (RAM_SIZE / 2))
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/* MMU page size */
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/* MMU page size */
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#define PAGE_SIZE 4096
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#define PAGE_SIZE 4096
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/* Number of DTLB sets used (power of 2, max is 256) */
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/* Number of DTLB sets used (power of 2, max is 256) */
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SPR_DTLBTR_SWE )
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SPR_DTLBTR_SWE )
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/* fails if x is false */
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/* fails if x is false */
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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#define TEST_JUMP(x)
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/* Extern functions */
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/* Extern functions */
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extern void lo_dmmu_en (void);
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extern void lo_dmmu_en (void);
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extern void lo_immu_en (void);
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extern void lo_immu_en (void);
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/* Global variables */
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/* Global variables */
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Line 109... |
}
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}
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}
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}
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printf("ea = %.8lx set = %d way = %d\n", ea, set, way);
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printf("ea = %.8lx set = %d way = %d\n", ea, set, way);
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if ((RAM_START <= ea) && (ea < CODE_END_ADD)) {
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if ((RAM_START <= ea) && (ea < DATA_END_ADD)) {
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/* If this is acces to data of this program set one to one translation */
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/* If this is acces to data of this program set one to one translation */
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mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | TLB_PR_NOLIMIT);
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mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | TLB_PR_NOLIMIT);
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return;
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return;
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}
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}
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/* Update DTLB miss counter and EA */
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/* Update DTLB miss counter and EA */
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dtlb_miss_count++;
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dtlb_miss_count++;
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dtlb_miss_ea = ea;
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dtlb_miss_ea = ea;
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/* Whatever access is in progress, translated address have to point to physical RAM */
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/* Whatever access is in progress, translated address have to point to physical RAM */
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ta = (ea & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2);
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ta = (ea & ((RAM_SIZE/2) - 1)) + DATA_END_ADD;
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printf("ta = %.8lx\n", ta);
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printf("ta = %.8lx\n", ta);
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/* Set appropriate TLB entry */
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/* Set appropriate TLB entry */
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switch (dtlb_val & TLB_CODE_MASK) {
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switch (dtlb_val & TLB_CODE_MASK) {
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case TLB_CODE_ONE_TO_ONE:
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case TLB_CODE_ONE_TO_ONE:
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Line 157... |
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/* ITLB miss exception handler */
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/* ITLB miss exception handler */
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void itlb_miss_handler (void)
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void itlb_miss_handler (void)
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{
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{
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unsigned long ea, ta, tlbtr;
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int set, way = 0;
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int i;
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/* Get EA that cause the exception */
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ea = mfspr (SPR_EEAR_BASE);
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/* Find TLB set and LRU way */
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set = (ea / PAGE_SIZE) % ITLB_SETS;
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for (i = 0; i < ITLB_WAYS; i++) {
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if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_LRU) == 0) {
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way = i;
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break;
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}
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}
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printf("ea = %.8lx set = %d way = %d\n", ea, set, way);
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if ((FLASH_START <= ea) && (ea < TEXT_END_ADD)) {
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/* If this is acces to data of this program set one to one translation */
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mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(way) + set, (ea & SPR_ITLBTR_PPN) | TLB_PR_NOLIMIT);
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return;
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}
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/* Update ITLB miss counter and EA */
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itlb_miss_count++;
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itlb_miss_ea = ea;
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/* Whatever access is in progress, translated address have to point to physical RAM */
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ta = (ea & ((FLASH_SIZE/2) - 1)) + TEXT_END_ADD;
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printf("ta = %.8lx\n", ta);
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/* Set appropriate TLB entry */
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switch (itlb_val & TLB_CODE_MASK) {
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case TLB_CODE_ONE_TO_ONE:
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tlbtr = (ta & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
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printf("1: tlbtr = %.8lx\n", tlbtr);
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break;
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case TLB_CODE_PLUS_ONE_PAGE:
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if ((ta + PAGE_SIZE) >= (FLASH_START + FLASH_SIZE))
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/* Wrapp last page */
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tlbtr = (((ta & ((FLASH_SIZE/2) - 1)) + TEXT_END_ADD) & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
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else
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tlbtr = ((ta + PAGE_SIZE) & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
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printf("2: tlbtr = %.8lx\n", tlbtr);
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break;
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case TLB_CODE_MINUS_ONE_PAGE:
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if ((ta - PAGE_SIZE) < TEXT_END_ADD)
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/* Wrapp first page */
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tlbtr = ((ta - PAGE_SIZE + (FLASH_SIZE/2)) & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
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else
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tlbtr = ((ta - PAGE_SIZE) & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
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printf("3: tlbtr = %.8lx\n", tlbtr);
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break;
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}
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/* Set ITLB entry */
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mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(way) + set, tlbtr);
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}
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}
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/* Invalidate all entries in DTLB and enable DMMU */
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/* Invalidate all entries in DTLB and enable DMMU */
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void dmmu_enable (void)
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void dmmu_enable (void)
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{
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{
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Line 329... |
}
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}
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return 0;
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return 0;
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}
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}
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/* Valid bit test
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Set all ways of one set to be invalid, perform
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access so miss handler will set them to valid,
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try access again - there should be no miss exceptions */
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int itlb_valid_bit_test (int set)
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{
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int i;
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/* Reset ITLB miss counter and EA */
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itlb_miss_count = 0;
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itlb_miss_ea = 0;
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/* Set itlb permisions */
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itlb_val = TLB_PR_NOLIMIT;
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/* Resetv ITLBMR for every way */
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for (i = 0; i < ITLB_WAYS; i++) {
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mtspr (SPR_ITLBMR_BASE(i) + set, 0);
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}
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/* Perform jumps to address, that is not in ITLB */
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for (i = 0; i < ITLB_WAYS; i++) {
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TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
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/* Check if there was ITLB miss */
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ASSERT(itlb_miss_count == (i + 1));
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ASSERT(itlb_miss_ea == (FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
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}
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/* Reset ITLB miss counter and EA */
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itlb_miss_count = 0;
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itlb_miss_ea = 0;
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/* Perform jumps to address, that is now in ITLB */
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for (i = 0; i < ITLB_WAYS; i++) {
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TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
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/* Check if there was ITLB miss */
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ASSERT(itlb_miss_count == 0);
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}
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/* Reset valid bits */
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for (i = 0; i < ITLB_WAYS; i++) {
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mtspr (SPR_ITLBMR_BASE(i) + set, mfspr (SPR_ITLBMR_BASE(i) + set) & ~SPR_ITLBMR_V);
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}
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/* Perform jumps to address, that is now in ITLB but is invalid */
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for (i = 0; i < ITLB_WAYS; i++) {
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TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
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/* Check if there was ITLB miss */
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ASSERT(itlb_miss_count == (i + 1));
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ASSERT(itlb_miss_ea == (FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
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}
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return 0;
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}
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int main (void)
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int main (void)
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{
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{
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int i;
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int i;
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Line 398... |
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/* Valid bit testing */
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/* Valid bit testing */
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for (i = 0; i < 15; i++)
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for (i = 0; i < 15; i++)
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dtlb_valid_bit_test (DTLB_SETS - i - 1);
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dtlb_valid_bit_test (DTLB_SETS - i - 1);
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/* Valid bit testing */
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for (i = 0; i < 15; i++)
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itlb_valid_bit_test (ITLB_SETS - i - 1);
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/* Write pattern */
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/* Write pattern */
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// write_pattern(0x40000000, 0x40100000);
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// write_pattern(0x40000000, 0x40100000);
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/* Enable IMMU */
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/* Enable IMMU */
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// immu_enable();
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// immu_enable();
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