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Line 66... |
#include "dumpverilog.h"
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#include "dumpverilog.h"
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#include "trace.h"
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#include "trace.h"
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#include "cuc.h"
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#include "cuc.h"
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/* CVS revision number. */
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/* CVS revision number. */
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const char rcsrev[] = "$Revision: 1.124 $";
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const char rcsrev[] = "$Revision: 1.125 $";
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inline void debug(int level, const char *format, ...)
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inline void debug(int level, const char *format, ...)
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{
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{
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char *p;
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char *p;
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va_list ap;
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va_list ap;
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| Line 99... |
Line 99... |
}
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}
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void ctrl_c(signum)
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void ctrl_c(signum)
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int signum;
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int signum;
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{
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{
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runtime.sim.cont_run = runtime.cpu.stalled ? 0 : 1;
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runtime.sim.iprompt = 1;
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runtime.sim.iprompt = 1;
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set_stall_state (0);
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signal(SIGINT, ctrl_c);
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signal(SIGINT, ctrl_c);
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}
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}
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void version()
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/* Periodically checks runtime.sim.iprompt to see if ctrl_c has been pressed */
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void check_int(void *dat)
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{
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if(runtime.sim.iprompt) {
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set_stall_state (0);
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handle_sim_command();
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}
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SCHED_ADD(check_int, NULL, CHECK_INT_TIME);
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}
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void version(void)
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{
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{
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PRINTF ("\n");
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PRINTF ("\n");
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PRINTF ("OpenRISC 1000 (OR32) Architectural Simulator, %s\n", rcsrev);
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PRINTF ("OpenRISC 1000 (OR32) Architectural Simulator, %s\n", rcsrev);
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PRINTF ("Copyright (C) 1999 Damjan Lampret, lampret@opencores.org\n");
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PRINTF ("Copyright (C) 1999 Damjan Lampret, lampret@opencores.org\n");
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PRINTF ("Copyright (C) 2000 Damjan Lampret, lampret@opencores.org\n");
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PRINTF ("Copyright (C) 2000 Damjan Lampret, lampret@opencores.org\n");
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Line 176... |
tick_reset();
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tick_reset();
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pm_reset();
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pm_reset();
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pic_reset();
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pic_reset();
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du_reset ();
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du_reset ();
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/* Make sure that runtime.sim.iprompt is the first thing to get checked */
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SCHED_ADD(check_int, NULL, 0);
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lock_memory_table ();
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lock_memory_table ();
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/* FIXME: Lame-ass way to get runtime.sim.mem_cycles not going into overly
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/* FIXME: Lame-ass way to get runtime.sim.mem_cycles not going into overly
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* negative numbers. This happens because parse.c uses setsim_mem32 to load
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* negative numbers. This happens because parse.c uses setsim_mem32 to load
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* the program but set_mem32 calls dc_simulate_write, which inturn calls
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* the program but set_mem32 calls dc_simulate_write, which inturn calls
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| Line 365... |
Line 376... |
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tmp->func (tmp->param);
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tmp->func (tmp->param);
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} while (scheduler.job_queue->time <= 0);
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} while (scheduler.job_queue->time <= 0);
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}
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}
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void recalc_do_stats(void)
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{
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extern int do_stats;
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do_stats = config.cpu.dependstats || config.cpu.superscalar ||
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config.cpu.dependstats || config.sim.history || config.sim.exe_log;
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}
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/* Main function */
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/* Main function */
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int main(argc, argv)
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int main(argc, argv)
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int argc;
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int argc;
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char *argv[];
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char *argv[];
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{
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{
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| Line 401... |
Line 419... |
if (runtime.simcmd.mprofile) config.sim.mprofile = 1;
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if (runtime.simcmd.mprofile) config.sim.mprofile = 1;
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if (!runtime.sim.script_file_specified && config.sim.verbose)
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if (!runtime.sim.script_file_specified && config.sim.verbose)
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fprintf (stderr, "WARNING: No config file read, assuming default configuration.\n");
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fprintf (stderr, "WARNING: No config file read, assuming default configuration.\n");
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print_config();
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print_config();
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sim_init ();
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signal(SIGINT, ctrl_c);
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signal(SIGINT, ctrl_c);
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runtime.sim.hush = 1;
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runtime.sim.hush = 1;
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runtime.sim.cont_run = -1;
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recalc_do_stats();
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while(1) {
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sim_init ();
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if (runtime.sim.iprompt)
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handle_sim_command();
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{ /* Needed by execution */
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extern int do_stats;
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do_stats = config.cpu.dependstats || config.cpu.superscalar || config.cpu.dependstats
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|| config.sim.history || config.sim.exe_log;
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}
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/* MM: 'run -1' means endless execution. */
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while(1) {
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while(runtime.sim.cont_run) {
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long long time_start = runtime.sim.cycles;
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long long time_start = runtime.sim.cycles;
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if (config.debug.enabled) {
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if (config.debug.enabled) {
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du_clock(); // reset watchpoints
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du_clock(); // reset watchpoints
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if (runtime.cpu.stalled) {
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while (runtime.cpu.stalled) {
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if(config.debug.gdb_enabled) {
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if(config.debug.gdb_enabled) {
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BlockJTAG();
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BlockJTAG();
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HandleServerSocket(false);
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HandleServerSocket(false);
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} else {
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} else {
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fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.");
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fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.\n");
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runtime.sim.cont_run = 0;
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/* Dump the user into interactive mode. From there he can decide what
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* to do. */
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handle_sim_command();
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sim_done();
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}
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}
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continue;
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if(runtime.sim.iprompt)
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handle_sim_command();
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}
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}
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}
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}
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/* Each cycle has counter of mem_cycles; this value is joined with cycles
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/* Each cycle has counter of mem_cycles; this value is joined with cycles
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at the end of the cycle; no sim originated memory accesses should be
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at the end of the cycle; no sim originated memory accesses should be
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performed inbetween. */
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performed inbetween. */
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runtime.sim.mem_cycles = 0;
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runtime.sim.mem_cycles = 0;
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if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
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if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME))
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if (runtime.sim.cont_run > 0) runtime.sim.cont_run--;
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if (cpu_clock ())
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if (cpu_clock ()) break;
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/* A breakpoint has been hit, drop to interactive mode */
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}
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handle_sim_command();
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if (config.vapi.enabled && runtime.vapi.enabled) vapi_check();
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if (config.vapi.enabled && runtime.vapi.enabled) vapi_check();
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if (config.debug.gdb_enabled) HandleServerSocket(false); /* block & check_stdin = false */
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if (config.debug.gdb_enabled) HandleServerSocket(false); /* block & check_stdin = false */
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if(config.debug.enabled)
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if(config.debug.enabled)
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if (testsprbits(SPR_DMR1, SPR_DMR1_ST)) set_stall_state (1);
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if (testsprbits(SPR_DMR1, SPR_DMR1_ST)) set_stall_state (1);
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runtime.sim.cycles += runtime.sim.mem_cycles;
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runtime.sim.cycles += runtime.sim.mem_cycles;
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scheduler.job_queue->time -= runtime.sim.cycles - time_start;
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scheduler.job_queue->time -= runtime.sim.cycles - time_start;
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if (scheduler.job_queue->time <= 0) do_scheduler ();
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if (scheduler.job_queue->time <= 0) do_scheduler ();
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if (!runtime.sim.hush) dumpreg();
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}
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runtime.sim.hush = 0;
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fflush(stdout);
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runtime.sim.fout = stdout;
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if (!runtime.sim.iprompt) /* non-interactive quit */
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sim_done();
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}
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}
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sim_done();
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sim_done();
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}
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}
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No newline at end of file
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No newline at end of file
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