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Rev 318 |
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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
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// First import.
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//
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// Revision 1.1 2001/08/20 18:17:52 damjan
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// Revision 1.1 2001/08/20 18:17:52 damjan
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// Initial revision
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// Initial revision
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//
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//
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// Revision 1.1 2001/08/13 03:37:07 lampret
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// Revision 1.1 2001/08/13 03:37:07 lampret
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// Added monitor.v and timescale.v
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// Added monitor.v and timescale.v
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Line 179... |
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always @(posedge xess_top.i_xess_fpga.risc.cpu.id.clk)
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always @(posedge xess_top.i_xess_fpga.risc.cpu.id.clk)
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if (!xess_top.i_xess_fpga.risc.cpu.id.wb_freeze) begin
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if (!xess_top.i_xess_fpga.risc.cpu.id.wb_freeze) begin
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#2;
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#2;
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if ((xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1500ffff) && (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14000000)
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if ((xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1500ffff) && (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14000000)
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&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14004444))
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&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14004444)
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&& !(xess_top.i_xess_fpga.risc.cpu.except.except_flushpipe && xess_top.i_xess_fpga.risc.cpu.except.ex_dslot))
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display_arch_state;
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display_arch_state;
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if (xess_top.i_xess_fpga.risc.cpu.id.ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)
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if (xess_top.i_xess_fpga.risc.cpu.id.ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)
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caught_sys203;
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caught_sys203;
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end
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end
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