| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/01/19 14:10:39 lampret
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// Fixed OR1200_XILINX_RAM32X1D.
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//
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// Revision 1.6 2002/01/18 07:57:56 lampret
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// Revision 1.6 2002/01/18 07:57:56 lampret
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// Added support for reading XILINX_RAM32X1D register file.
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// Added support for reading XILINX_RAM32X1D register file.
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//
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//
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// Revision 1.5 2002/01/14 06:19:35 lampret
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// Revision 1.5 2002/01/14 06:19:35 lampret
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// Added debug model for testing du. Updated or1200_monitor.
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// Added debug model for testing du. Updated or1200_monitor.
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| Line 203... |
Line 206... |
// - access to SPRs
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// - access to SPRs
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//
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//
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always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
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always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
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if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
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if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
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#2;
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#2;
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if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[0])
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if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
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&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
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&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
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display_arch_state;
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display_arch_state;
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
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get_gpr(3, r3);
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get_gpr(3, r3);
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$fdisplay(fnop, "%t: l.nop exit (%h)", $time, r3);
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$fdisplay(fnop, "%t: l.nop exit (%h)", $time, r3);
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