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Rev 1063 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.27 2002/09/16 03:13:23 lampret
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// Removed obsolete comment.
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//
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// Revision 1.26 2002/09/08 05:52:16 lampret
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// Revision 1.26 2002/09/08 05:52:16 lampret
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// Added optional l.div/l.divu insns. By default they are disabled.
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// Added optional l.div/l.divu insns. By default they are disabled.
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//
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//
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// Revision 1.25 2002/09/07 19:16:10 lampret
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// Revision 1.25 2002/09/07 19:16:10 lampret
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// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
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// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
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//
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//
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// Do not change below unless you know what you are doing
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// Do not change below unless you know what you are doing
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//
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//
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//
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//
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// Enable RAM BIST
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//
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// At the moment this only works for Virtual Silicon
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// single port RAMs. For other RAMs it has not effect.
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// Special wrapper for VS RAMs needs to be provided
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// with scan flops to facilitate bist scan.
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//
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//`define OR1200_BIST
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//
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// Register OR1200 WISHBONE outputs
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// Register OR1200 WISHBONE outputs
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// (must be defined/enabled)
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// (must be defined/enabled)
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//
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//
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`define OR1200_REGISTERED_OUTPUTS
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`define OR1200_REGISTERED_OUTPUTS
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