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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.30 2002/10/28 15:09:22 mohor
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// Previous check-in was done by mistake.
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//
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// Revision 1.29 2002/10/28 15:03:50 mohor
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// Revision 1.29 2002/10/28 15:03:50 mohor
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// Signal scanb_sen renamed to scanb_en.
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// Signal scanb_sen renamed to scanb_en.
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//
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//
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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Line 353... |
Line 356... |
// undefine this macro.
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// undefine this macro.
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//
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//
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//`define OR1200_WB_RETRY 7
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//`define OR1200_WB_RETRY 7
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//
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//
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// WISHBONE Consecutive Address Burst
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//
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// This was used prior to WISHBONE B3 specification
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// to identify bursts. It is no longer needed but
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// remains enabled for compatibility with old designs.
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//
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// To remove *wb_cab_o ports undefine this macro.
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//
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`define OR1200_WB_CAB
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//
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// WISHBONE B3 compatible interface
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//
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// This follows the WISHBONE B3 specification.
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// It is not enabled by default because most
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// designs still don't use WB b3.
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//
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// To enable *wb_cti_o/*wb_bte_o ports,
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// define this macro.
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//
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//`define OR1200_WB_B3
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//
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// Enable additional synthesis directives if using
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// Enable additional synthesis directives if using
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// _Synopsys_ synthesis tool
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// _Synopsys_ synthesis tool
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//
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//
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//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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