| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.36 2003/10/17 07:59:44 markom
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// Revision 1.35.4.6 2004/02/11 01:40:11 lampret
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// mbist signals updated according to newest convention
|
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.35.4.5 2004/01/15 06:46:38 markom
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|
// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
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// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
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//
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// Revision 1.35.4.3 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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//
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// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
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// Static exception prefix.
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//
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// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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//
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// Revision 1.35 2003/04/24 00:16:07 lampret
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// Revision 1.35 2003/04/24 00:16:07 lampret
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// No functional changes. Added defines to disable implementation of multiplier/MAC
|
// No functional changes. Added defines to disable implementation of multiplier/MAC
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//
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//
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// Revision 1.34 2003/04/20 22:23:57 lampret
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// Revision 1.34 2003/04/20 22:23:57 lampret
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| Line 64... |
Line 79... |
//
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//
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// Revision 1.30 2002/10/28 15:09:22 mohor
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// Revision 1.30 2002/10/28 15:09:22 mohor
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// Previous check-in was done by mistake.
|
// Previous check-in was done by mistake.
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//
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//
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// Revision 1.29 2002/10/28 15:03:50 mohor
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// Revision 1.29 2002/10/28 15:03:50 mohor
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// Signal mbist_sen renamed to mbist_ctrl_i.
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// Signal scanb_sen renamed to scanb_en.
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//
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//
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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//
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// Revision 1.27 2002/09/16 03:13:23 lampret
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// Revision 1.27 2002/09/16 03:13:23 lampret
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| Line 341... |
Line 356... |
// Special wrapper for VS RAMs needs to be provided
|
// Special wrapper for VS RAMs needs to be provided
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// with scan flops to facilitate bist scan.
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// with scan flops to facilitate bist scan.
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//
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//
|
//`define OR1200_BIST
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//`define OR1200_BIST
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// width of MBIST control bus
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|
`define OR1200_MBIST_CTRL_WIDTH 3
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|
|
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//
|
//
|
// Register OR1200 WISHBONE outputs
|
// Register OR1200 WISHBONE outputs
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// (must be defined/enabled)
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// (must be defined/enabled)
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//
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//
|
`define OR1200_REGISTERED_OUTPUTS
|
`define OR1200_REGISTERED_OUTPUTS
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| Line 438... |
Line 450... |
// save area.
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// save area.
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//
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//
|
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
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//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
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//
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//
|
// Implement l.addc/l.addic instructions and SR[CY]
|
// Implement l.addc/l.addic instructions
|
//
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|
// At the time of writing this, or32
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|
// C/C++ compiler doesn't generate l.addc/l.addic
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// instructions. However or32 assembler
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|
// can assemble code that uses l.addc/l.addic insns.
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//
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//
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// By default implementation of l.addc/l.addic
|
// By default implementation of l.addc/l.addic
|
// instructions and SR[CY] is disabled to save
|
// instructions is enabled in case you need them.
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// area.
|
// If you don't use them, then disable implementation
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// to save area.
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//
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|
`define OR1200_IMPL_ADDC
|
|
|
//
|
//
|
// [Because this define controles implementation
|
// Implement carry bit SR[CY]
|
// of SR[CY] write enable, if it is not enabled,
|
|
// l.add/l.addi also don't set SR[CY].]
|
|
//
|
//
|
//`define OR1200_IMPL_ADDC
|
// By default implementation of SR[CY] is enabled
|
|
// to be compliant with the simulator. However
|
|
// SR[CY] is explicitly only used by l.addc/l.addic
|
|
// instructions and if these two insns are not
|
|
// implemented there is not much point having SR[CY].
|
|
//
|
|
`define OR1200_IMPL_CY
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|
|
//
|
//
|
// Implement optional l.div/l.divu instructions
|
// Implement optional l.div/l.divu instructions
|
//
|
//
|
// By default divide instructions are not implemented
|
// By default divide instructions are not implemented
|
| Line 867... |
Line 882... |
`define OR1200_SR_DSX 13 // Unused
|
`define OR1200_SR_DSX 13 // Unused
|
`define OR1200_SR_EPH 14
|
`define OR1200_SR_EPH 14
|
`define OR1200_SR_FO 15
|
`define OR1200_SR_FO 15
|
`define OR1200_SR_CID 31:28 // Unimplemented
|
`define OR1200_SR_CID 31:28 // Unimplemented
|
|
|
|
//
|
// Bits that define offset inside the group
|
// Bits that define offset inside the group
|
|
//
|
`define OR1200_SPROFS_BITS 10:0
|
`define OR1200_SPROFS_BITS 10:0
|
|
|
//
|
//
|
// Default Exception Prefix
|
// Default Exception Prefix
|
//
|
//
|
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
|
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
|
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
|
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
|
//
|
//
|
`define OR1200_SR_EPH_DEF 1'b0
|
`define OR1200_SR_EPH_DEF 1'b0
|
|
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
//
|
//
|
// Power Management (PM)
|
// Power Management (PM)
|
//
|
//
|
|
|
| Line 918... |
Line 934... |
//
|
//
|
|
|
// Define it if you want DU implemented
|
// Define it if you want DU implemented
|
`define OR1200_DU_IMPLEMENTED
|
`define OR1200_DU_IMPLEMENTED
|
|
|
|
//
|
|
// Define if you want HW Breakpoints
|
|
// (if HW breakpoints are not implemented
|
|
// only default software trapping is
|
|
// possible with l.trap insn - this is
|
|
// however already enough for use
|
|
// with or32 gdb)
|
|
//
|
|
//`define OR1200_DU_HWBKPTS
|
|
|
|
// Number of DVR/DCR pairs if HW breakpoints enabled
|
|
`define OR1200_DU_DVRDCR_PAIRS 8
|
|
|
// Define if you want trace buffer
|
// Define if you want trace buffer
|
// (for now only available for Xilinx Virtex FPGAs)
|
// (for now only available for Xilinx Virtex FPGAs)
|
`ifdef OR1200_ASIC
|
`ifdef OR1200_ASIC
|
`else
|
`else
|
`define OR1200_DU_TB_IMPLEMENTED
|
`define OR1200_DU_TB_IMPLEMENTED
|
`endif
|
`endif
|
|
|
|
//
|
// Address offsets of DU registers inside DU group
|
// Address offsets of DU registers inside DU group
|
`define OR1200_DU_OFS_DMR1 11'd16
|
//
|
`define OR1200_DU_OFS_DMR2 11'd17
|
// To not implement a register, do not define its address
|
`define OR1200_DU_OFS_DSR 11'd20
|
//
|
`define OR1200_DU_OFS_DRR 11'd21
|
`ifdef OR1200_DU_HWBKPTS
|
`define OR1200_DU_OFS_TBADR 11'h0ff
|
`define OR1200_DU_DVR0 11'd0
|
`define OR1200_DU_OFS_TBIA 11'h1xx
|
`define OR1200_DU_DVR1 11'd1
|
`define OR1200_DU_OFS_TBIM 11'h2xx
|
`define OR1200_DU_DVR2 11'd2
|
`define OR1200_DU_OFS_TBAR 11'h3xx
|
`define OR1200_DU_DVR3 11'd3
|
`define OR1200_DU_OFS_TBTS 11'h4xx
|
`define OR1200_DU_DVR4 11'd4
|
|
`define OR1200_DU_DVR5 11'd5
|
|
`define OR1200_DU_DVR6 11'd6
|
|
`define OR1200_DU_DVR7 11'd7
|
|
`define OR1200_DU_DCR0 11'd8
|
|
`define OR1200_DU_DCR1 11'd9
|
|
`define OR1200_DU_DCR2 11'd10
|
|
`define OR1200_DU_DCR3 11'd11
|
|
`define OR1200_DU_DCR4 11'd12
|
|
`define OR1200_DU_DCR5 11'd13
|
|
`define OR1200_DU_DCR6 11'd14
|
|
`define OR1200_DU_DCR7 11'd15
|
|
`endif
|
|
`define OR1200_DU_DMR1 11'd16
|
|
`ifdef OR1200_DU_HWBKPTS
|
|
`define OR1200_DU_DMR2 11'd17
|
|
`define OR1200_DU_DWCR0 11'd18
|
|
`define OR1200_DU_DWCR1 11'd19
|
|
`endif
|
|
`define OR1200_DU_DSR 11'd20
|
|
`define OR1200_DU_DRR 11'd21
|
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
|
`define OR1200_DU_TBADR 11'h0ff
|
|
`define OR1200_DU_TBIA 11'h1xx
|
|
`define OR1200_DU_TBIM 11'h2xx
|
|
`define OR1200_DU_TBAR 11'h3xx
|
|
`define OR1200_DU_TBTS 11'h4xx
|
|
`endif
|
|
|
// Position of offset bits inside SPR address
|
// Position of offset bits inside SPR address
|
`define OR1200_DUOFS_BITS 10:0
|
`define OR1200_DUOFS_BITS 10:0
|
|
|
// Define if you want these DU registers to be implemented
|
// DCR bits
|
`define OR1200_DU_DMR1
|
`define OR1200_DU_DCR_DP 0
|
`define OR1200_DU_DMR2
|
`define OR1200_DU_DCR_CC 3:1
|
`define OR1200_DU_DSR
|
`define OR1200_DU_DCR_SC 4
|
`define OR1200_DU_DRR
|
`define OR1200_DU_DCR_CT 7:5
|
|
|
// DMR1 bits
|
// DMR1 bits
|
|
`define OR1200_DU_DMR1_CW0 1:0
|
|
`define OR1200_DU_DMR1_CW1 3:2
|
|
`define OR1200_DU_DMR1_CW2 5:4
|
|
`define OR1200_DU_DMR1_CW3 7:6
|
|
`define OR1200_DU_DMR1_CW4 9:8
|
|
`define OR1200_DU_DMR1_CW5 11:10
|
|
`define OR1200_DU_DMR1_CW6 13:12
|
|
`define OR1200_DU_DMR1_CW7 15:14
|
|
`define OR1200_DU_DMR1_CW8 17:16
|
|
`define OR1200_DU_DMR1_CW9 19:18
|
|
`define OR1200_DU_DMR1_CW10 21:20
|
`define OR1200_DU_DMR1_ST 22
|
`define OR1200_DU_DMR1_ST 22
|
|
`define OR1200_DU_DMR1_BT 23
|
|
`define OR1200_DU_DMR1_DXFW 24
|
|
`define OR1200_DU_DMR1_ETE 25
|
|
|
|
// DMR2 bits
|
|
`define OR1200_DU_DMR2_WCE0 0
|
|
`define OR1200_DU_DMR2_WCE1 1
|
|
`define OR1200_DU_DMR2_AWTC 12:2
|
|
`define OR1200_DU_DMR2_WGB 23:13
|
|
|
|
// DWCR bits
|
|
`define OR1200_DU_DWCR_COUNT 15:0
|
|
`define OR1200_DU_DWCR_MATCH 31:16
|
|
|
// DSR bits
|
// DSR bits
|
`define OR1200_DU_DSR_WIDTH 14
|
`define OR1200_DU_DSR_WIDTH 14
|
`define OR1200_DU_DSR_RSTE 0
|
`define OR1200_DU_DSR_RSTE 0
|
`define OR1200_DU_DSR_BUSEE 1
|
`define OR1200_DU_DSR_BUSEE 1
|
| Line 987... |
Line 1068... |
`define OR1200_DU_READREGS
|
`define OR1200_DU_READREGS
|
|
|
// Define if unused DU registers bits should be zero
|
// Define if unused DU registers bits should be zero
|
`define OR1200_DU_UNUSED_ZERO
|
`define OR1200_DU_UNUSED_ZERO
|
|
|
// DU operation commands
|
|
`define OR1200_DU_OP_READSPR 3'd4
|
|
`define OR1200_DU_OP_WRITESPR 3'd5
|
|
|
|
// Define if IF/LSU status is not needed by devel i/f
|
// Define if IF/LSU status is not needed by devel i/f
|
`define OR1200_DU_STATUS_UNIMPLEMENTED
|
`define OR1200_DU_STATUS_UNIMPLEMENTED
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
//
|
//
|
| Line 1285... |
Line 1362... |
//
|
//
|
`define OR1200_SB_LOG 2 // 2 or 3
|
`define OR1200_SB_LOG 2 // 2 or 3
|
`define OR1200_SB_ENTRIES 4 // 4 or 8
|
`define OR1200_SB_ENTRIES 4 // 4 or 8
|
|
|
|
|
|
/////////////////////////////////////////////////
|
|
//
|
|
// Quick Embedded Memory (QMEM)
|
|
//
|
|
|
|
//
|
|
// Quick Embedded Memory
|
|
//
|
|
// Instantiation of dedicated insn/data memory (RAM or ROM).
|
|
// Insn fetch has effective throughput 1insn / clock cycle.
|
|
// Data load takes two clock cycles / access, data store
|
|
// takes 1 clock cycle / access (if there is no insn fetch)).
|
|
// Memory instantiation is shared between insn and data,
|
|
// meaning if insn fetch are performed, data load/store
|
|
// performance will be lower.
|
|
//
|
|
// Main reason for QMEM is to put some time critical functions
|
|
// into this memory and to have predictable and fast access
|
|
// to these functions. (soft fpu, context switch, exception
|
|
// handlers, stack, etc)
|
|
//
|
|
// It makes design a bit bigger and slower. QMEM sits behind
|
|
// IMMU/DMMU so all addresses are physical (so the MMUs can be
|
|
// used with QMEM and QMEM is seen by the CPU just like any other
|
|
// memory in the system). IC/DC are sitting behind QMEM so the
|
|
// whole design timing might be worse with QMEM implemented.
|
|
//
|
|
`define OR1200_QMEM_IMPLEMENTED
|
|
|
|
//
|
|
// Base address and mask of QMEM
|
|
//
|
|
// Base address defines first address of QMEM. Mask defines
|
|
// QMEM range in address space. Actual size of QMEM is however
|
|
// determined with instantiated RAM/ROM. However bigger
|
|
// mask will reserve more address space for QMEM, but also
|
|
// make design faster, while more tight mask will take
|
|
// less address space but also make design slower. If
|
|
// instantiated RAM/ROM is smaller than space reserved with
|
|
// the mask, instatiated RAM/ROM will also be shadowed
|
|
// at higher addresses in reserved space.
|
|
//
|
|
`define OR1200_QMEM_IADDR 32'h0080_0000
|
|
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
|
|
`define OR1200_QMEM_DADDR 32'h0080_0000
|
|
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
|
|
|
|
//
|
|
// QMEM interface byte-select capability
|
|
//
|
|
// To enable qmem_sel* ports, define this macro.
|
|
//
|
|
//`define OR1200_QMEM_BSEL
|
|
|
|
//
|
|
// QMEM interface acknowledge
|
|
//
|
|
// To enable qmem_ack port, define this macro.
|
|
//
|
|
//`define OR1200_QMEM_ACK
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
//
|
//
|
// VR, UPR and Configuration Registers
|
// VR, UPR and Configuration Registers
|
//
|
//
|
//
|
//
|
| Line 1324... |
Line 1462... |
`define OR1200_VR_RES1_BITS 15:6
|
`define OR1200_VR_RES1_BITS 15:6
|
`define OR1200_VR_CFG_BITS 23:16
|
`define OR1200_VR_CFG_BITS 23:16
|
`define OR1200_VR_VER_BITS 31:24
|
`define OR1200_VR_VER_BITS 31:24
|
|
|
// VR values
|
// VR values
|
`define OR1200_VR_REV 6'h00
|
`define OR1200_VR_REV 6'h01
|
`define OR1200_VR_RES1 10'h000
|
`define OR1200_VR_RES1 10'h000
|
`define OR1200_VR_CFG 8'h00
|
`define OR1200_VR_CFG 8'h00
|
`define OR1200_VR_VER 8'h12
|
`define OR1200_VR_VER 8'h12
|
|
|
// UPR fields
|
// UPR fields
|
| Line 1559... |
Line 1697... |
`define OR1200_DCFGR_NDP_BITS 2:0
|
`define OR1200_DCFGR_NDP_BITS 2:0
|
`define OR1200_DCFGR_WPCI_BITS 3
|
`define OR1200_DCFGR_WPCI_BITS 3
|
`define OR1200_DCFGR_RES1_BITS 31:4
|
`define OR1200_DCFGR_RES1_BITS 31:4
|
|
|
// DCFGR values
|
// DCFGR values
|
|
`ifdef OR1200_DU_HWBKPTS
|
|
`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
|
|
`ifdef OR1200_DU_DWCR0
|
|
`define OR1200_DCFGR_WPCI 1'b1
|
|
`else
|
|
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
|
|
`endif
|
|
`else
|
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
|
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
|
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
|
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
|
|
`endif
|
`define OR1200_DCFGR_RES1 28'h0000000
|
`define OR1200_DCFGR_RES1 28'h0000000
|
|
|
No newline at end of file
|
No newline at end of file
|
