| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.43 2005/01/07 09:23:39 andreje
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// l.ff1 and l.cmov instructions added
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//
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// Revision 1.42 2004/06/08 18:17:36 lampret
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// Revision 1.42 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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// Non-functional changes. Coding style fixes.
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//
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//
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// Revision 1.41 2004/05/09 20:03:20 lampret
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// Revision 1.41 2004/05/09 20:03:20 lampret
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// By default l.cust5 insns are disabled
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// By default l.cust5 insns are disabled
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| Line 313... |
Line 316... |
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//
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//
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// Target FPGA memories
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// Target FPGA memories
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//
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//
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//`define OR1200_ALTERA_LPM
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//`define OR1200_ALTERA_LPM
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//`define OR1200_XILINX_RAMB16
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//`define OR1200_XILINX_RAMB4
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//`define OR1200_XILINX_RAMB4
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//`define OR1200_XILINX_RAM32X1D
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//`define OR1200_XILINX_RAM32X1D
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//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
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//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
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|
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//
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//
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| Line 968... |
Line 972... |
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// Number of DVR/DCR pairs if HW breakpoints enabled
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// Number of DVR/DCR pairs if HW breakpoints enabled
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`define OR1200_DU_DVRDCR_PAIRS 8
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`define OR1200_DU_DVRDCR_PAIRS 8
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// Define if you want trace buffer
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// Define if you want trace buffer
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// (for now only available for Xilinx Virtex FPGAs)
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`ifdef OR1200_ASIC
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`else
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//`define OR1200_DU_TB_IMPLEMENTED
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//`define OR1200_DU_TB_IMPLEMENTED
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`endif
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//
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//
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// Address offsets of DU registers inside DU group
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// Address offsets of DU registers inside DU group
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//
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//
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// To not implement a register, doq not define its address
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// To not implement a register, doq not define its address
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