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[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x8.v] - Diff between revs 1267 and 1291

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Rev 1267 Rev 1291
Line 61... Line 61... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.7  2004/04/05 08:29:57  lampret
 
 
 
// Merged branch_qmem into main tree.
 
 
 
//
 
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
 
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
 
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
 
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
 
//
 
//
 
// Revision 1.3  2003/04/07 01:19:07  lampret
 
// Revision 1.3  2003/04/07 01:19:07  lampret
 
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
 
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
Line 104... Line 107... 
`ifdef OR1200_BIST
 
`ifdef OR1200_BIST
 
        // RAM BIST
 
        // RAM BIST
 
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
`endif
 
`endif
 
        // Generic synchronous single-port RAM interface
 
        // Generic synchronous single-port RAM interface
 
        clk, rst, ce, we, oe, addr, di, do
 
        clk, rst, ce, we, oe, addr, di, doq
 
);
 
);
 
 
 
 
 
//
 
//
 
// Default address and data buses width
 
// Default address and data buses width
 
//
 
//
Line 132... Line 135... 
input                   ce;     // Chip enable input
 
input                   ce;     // Chip enable input
 
input                   we;     // Write enable input
 
input                   we;     // Write enable input
 
input                   oe;     // Output enable input
 
input                   oe;     // Output enable input
 
input   [aw-1:0] addr;   // address bus inputs
 
input   [aw-1:0] addr;   // address bus inputs
 
input   [dw-1:0] di;     // input data bus
 
input   [dw-1:0] di;     // input data bus
 
output  [dw-1:0] do;     // output data bus
 
output  [dw-1:0] doq;    // output data bus
 
 
 
 
 
//
 
//
 
// Internal wires and registers
 
// Internal wires and registers
 
//
 
//
 
 
 
 
Line 176... Line 179... 
        .CEN(~ce),
 
        .CEN(~ce),
 
        .WEN(~we),
 
        .WEN(~we),
 
        .A(addr),
 
        .A(addr),
 
        .D(di),
 
        .D(di),
 
        .OEN(~oe),
 
        .OEN(~oe),
 
        .Q(do)
 
        .Q(doq)
 
);
 
);
 
 
 
 
 
`else
 
`else
 
 
 
 
 
`ifdef OR1200_AVANT_ATP
 
`ifdef OR1200_AVANT_ATP
Line 197... Line 200... 
        .rcsb(),
 
        .rcsb(),
 
        .wcsb(),
 
        .wcsb(),
 
        .ra(addr),
 
        .ra(addr),
 
        .wa(addr),
 
        .wa(addr),
 
        .di(di),
 
        .di(di),
 
        .do(do)
 
        .doq(doq)
 
);
 
);
 
 
 
 
 
`else
 
`else
 
 
 
 
 
`ifdef OR1200_VIRAGE_SSP
 
`ifdef OR1200_VIRAGE_SSP
Line 216... Line 219... 
        .adr(addr),
 
        .adr(addr),
 
        .d(di),
 
        .d(di),
 
        .we(we),
 
        .we(we),
 
        .oe(oe),
 
        .oe(oe),
 
        .me(ce),
 
        .me(ce),
 
        .q(do)
 
        .q(doq)
 
);
 
);
 
 
 
 
 
`else
 
`else
 
 
 
 
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
`ifdef OR1200_VIRTUALSILICON_SSP
Line 249... Line 252... 
        .ADR(addr),
 
        .ADR(addr),
 
        .DI(di),
 
        .DI(di),
 
        .WEN(~we),
 
        .WEN(~we),
 
        .CEN(~ce),
 
        .CEN(~ce),
 
        .OEN(~oe),
 
        .OEN(~oe),
 
        .DOUT(do)
 
        .DOUT(doq)
 
);
 
);
 
 
 
 
 
`else
 
`else
 
 
 
 
 
`ifdef OR1200_XILINX_RAMB4
 
`ifdef OR1200_XILINX_RAMB4
Line 272... Line 275... 
        .RST(rst),
 
        .RST(rst),
 
        .ADDR(addr),
 
        .ADDR(addr),
 
        .DI(di[3:0]),
 
        .DI(di[3:0]),
 
        .EN(ce),
 
        .EN(ce),
 
        .WE(we),
 
        .WE(we),
 
        .DO(do[3:0])
 
        .DO(doq[3:0])
 
);
 
);
 
 
 
 
 
//
 
//
 
// Block 1
 
// Block 1
 
//
 
//
Line 285... Line 288... 
        .RST(rst),
 
        .RST(rst),
 
        .ADDR(addr),
 
        .ADDR(addr),
 
        .DI(di[7:4]),
 
        .DI(di[7:4]),
 
        .EN(ce),
 
        .EN(ce),
 
        .WE(we),
 
        .WE(we),
 
        .DO(do[7:4])
 
        .DO(doq[7:4])
 
);
 
);
 
 
 
 
 
`else
 
`else
 
 
 
 
 
`ifdef OR1200_ALTERA_LPM
 
`ifdef OR1200_ALTERA_LPM
Line 312... Line 315... 
        .address(addr),
 
        .address(addr),
 
        .inclock(clk),
 
        .inclock(clk),
 
        .outclock(clk),
 
        .outclock(clk),
 
        .data(di),
 
        .data(di),
 
        .we(wr),
 
        .we(wr),
 
        .q(do)
 
        .q(doq)
 
);
 
);
 
 
 
 
 
defparam lpm_ram_dq_component.lpm_width = dw,
 
defparam lpm_ram_dq_component.lpm_width = dw,
 
        lpm_ram_dq_component.lpm_widthad = aw,
 
        lpm_ram_dq_component.lpm_widthad = aw,
 
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
 
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
Line 333... Line 336... 
 
 
 
 
//
 
//
 
// Generic RAM's registers and wires
 
// Generic RAM's registers and wires
 
//
 
//
 
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
 
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
 
reg     [dw-1:0] do_reg;                 // RAM data output register
 
reg     [aw-1:0] addr_reg;               // RAM address register
 
 
 
 
 
//
 
//
 
// Data output drivers
 
// Data output drivers
 
//
 
//
 
assign do = (oe) ? do_reg : {dw{1'b0}};
 
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
 
 
 
 
 
 
//
 
 
 
// RAM address register
 
 
 
//
 
 
 
always @(posedge clk or posedge rst)
 
 
 
        if (rst)
 
 
 
                addr_reg <= #1 {aw{1'b0}};
 
 
 
        else if (ce)
 
 
 
                addr_reg <= #1 addr;
 
 
 
 
 
//
 
//
 
// RAM read and write
 
// RAM write
 
//
 
//
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce && !we)
 
        if (ce && we)
 
                do_reg <= #1 mem[addr];
 
 
 
        else if (ce && we)
 
 
 
                mem[addr] <= #1 di;
 
                mem[addr] <= #1 di;
 
 
 
 
 
`endif  // !OR1200_ALTERA_LPM
 
`endif  // !OR1200_ALTERA_LPM
 
`endif  // !OR1200_XILINX_RAMB4_S16
 
`endif  // !OR1200_XILINX_RAMB4_S16
 
`endif  // !OR1200_VIRTUALSILICON_SSP
 
`endif  // !OR1200_VIRTUALSILICON_SSP

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