Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2002/01/19 09:27:49 lampret
|
|
// SR[TEE] should be zero after reset.
|
|
//
|
// Revision 1.2 2002/01/18 07:56:00 lampret
|
// Revision 1.2 2002/01/18 07:56:00 lampret
|
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
|
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
|
//
|
//
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
Line 305... |
Line 308... |
//
|
//
|
// Supervision register
|
// Supervision register
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
sr <= #1 `OR1200_SR_WIDTH'b001;
|
sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
|
else if (except_started) begin
|
else if (except_started) begin
|
sr[`OR1200_SR_SM] <= #1 1'b1;
|
sr[`OR1200_SR_SM] <= #1 1'b1;
|
sr[`OR1200_SR_TEE] <= #1 1'b0;
|
sr[`OR1200_SR_TEE] <= #1 1'b0;
|
sr[`OR1200_SR_IEE] <= #1 1'b0;
|
sr[`OR1200_SR_IEE] <= #1 1'b0;
|
sr[`OR1200_SR_DME] <= #1 1'b0;
|
sr[`OR1200_SR_DME] <= #1 1'b0;
|