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This is OpenRISC 1000 and DLX architectural simulator. It was written by
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This is OpenRISC 1000 and DLX architectural simulator. It was written by
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Damjan Lampret and it is free software. See the file COPYING for copying
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Damjan Lampret and it is free software. See the file COPYING for copying
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permission. To contact the author, send mail to .
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permission. To contact the author, send mail to .
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I use it to define OR1K system architecture. An implementation simulator
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I use it to define OR1K system architecture. An implementation simulator
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for OR1K will be also available, probably in Nov/1999.
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for OR1K will be also available, probably in Mar/2000 or later.
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Initially this software was not meant to be released to public because it
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Initially this software was not meant to be released to public because it
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was developed just to analyze program flow of GCC generated assembly code.
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was developed just to analyze program flow of GCC generated assembly code.
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With the time it became bigger and was able to generate statistics about
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With the time it became bigger and was able to generate statistics about
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superscalar issuing of multiple instructions. I've used it as a test simulator
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superscalar issuing of multiple instructions. I've used it as a test simulator
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and it simulates the operation of instructions. Because it was meant to be used
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and it simulates the operation of instructions. Because it was meant to be used
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only to test characteristics of various RISC architectures and various GCC
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only to test characteristics of various RISC architectures and various GCC
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optimization methods, it has a bit strange memory model. It is abstract and
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optimization methods, it has a bit strange memory model. It is abstract and
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physical at the same time. I can't really explain, just check the sources if
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physical at the same time. I can't really explain, just check the sources if
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interested. Some other things are strange or incomplete too (like
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interested. Some other things are strange or incomplete too (like
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C library emulation, currently supports only printf).
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C library emulation, currently supports only printf via simprintf).
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cache and mmu directories are still empty. Someday (Nov/1999 probably) they
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MMMU directory is not functional. Someday (Nov/1999 probably) it
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will be filled with code for cache simulation and with code for virtual
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will be filled with code for virtual memory simulation.
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memory simulation.
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Installation
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Installation
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============
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============
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Simulator test
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Simulator test
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==============
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==============
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Issue 'or1ksim testbench/dhry.or1k' or 'dlxsim testbench/dhry.dlx' to
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Issue 'or1ksim testbench/dhry.or1k' or 'dlxsim testbench/dhry.dlx' to
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test simulator. Use 'help' to get list of simulator commands.
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test simulator. See testbench/README for details about Dhrystone 2.1
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Run simulation with 'run 1000000 hush'. It will take
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benchmark.
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a couple of seconds and you should get an error about label _exit.
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Now quit simulator with 'q' and open file stdout.txt. You should see
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output from simulated dhrystone benchmark.
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See testbench/README for details about Dhrystone 2.1 benchmark.
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OpenRISC and open cores
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OpenRISC and open cores
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=======================
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=======================
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About the same idea as with GNU project except we want free hardware
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About the same idea as with GNU project except we want free and open source
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IP (intellectual property). We design open source, synthesizeable
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IP (intellectual property) cores. We design open source, synthesizable
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cores. OpenRISC is one such core. It is a 32-bit RISC microprocessor that
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cores. OpenRISC is one such core. It is a 32-bit RISC microprocessor that
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will run GNU/Linux.
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will run GNU/Linux.
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For more information visit us at http://www.opencores.org.
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For more information visit us at http://www.opencores.org.
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--
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--
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24/Oct/1999, Damjan Lampret email:lampret@opencores.org
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29/Feb/2000, Damjan Lampret email:lampret@opencores.org
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29/Feb/2000, Damjan Lampret email:lampret@opencores.org
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