| Line 70... |
Line 70... |
/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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immu_stats.fetch_tlbhit++;
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immu_stats.fetch_tlbhit++;
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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|
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/* Test for page fault */
|
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if (mfspr (SPR_SR) & SPR_SR_SM) {
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
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except_handle(EXCEPT_IPF, virtaddr);
|
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} else {
|
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
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except_handle(EXCEPT_IPF, virtaddr);
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}
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|
|
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/* Set LRUs */
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/* Set LRUs */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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setsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU, config.immu.nsets - 1);
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setsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU, config.immu.nsets - 1);
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|
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
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insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
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|
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runtime.sim.mem_cycles += config.immu.hitdelay;
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runtime.sim.mem_cycles += config.immu.hitdelay;
|
|
|
|
/* Test for page fault */
|
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if (mfspr (SPR_SR) & SPR_SR_SM) {
|
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
|
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except_handle(EXCEPT_IPF, virtaddr);
|
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} else {
|
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if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
|
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except_handle(EXCEPT_IPF, virtaddr);
|
|
}
|
|
|
ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
|
ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
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return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
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return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
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}
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}
|
else { /* No, we didn't. */
|
else { /* No, we didn't. */
|
immu_stats.fetch_tlbmiss++;
|
immu_stats.fetch_tlbmiss++;
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| Line 107... |
Line 108... |
setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
|
setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
|
setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
|
setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
|
setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
|
setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
|
setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
|
setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
|
#endif
|
#endif
|
except_handle(EXCEPT_ITLBMISS, virtaddr);
|
|
/* if tlb refill implemented in HW */
|
/* if tlb refill implemented in HW */
|
/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
|
/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
|
runtime.sim.mem_cycles += config.immu.missdelay;
|
runtime.sim.mem_cycles += config.immu.missdelay;
|
|
|
|
except_handle(EXCEPT_ITLBMISS, virtaddr);
|
return 0;
|
return 0;
|
}
|
}
|
}
|
}
|
|
|
/* DESC: try to find EA -> PA transaltion without changing
|
/* DESC: try to find EA -> PA transaltion without changing
|
